Patents by Inventor Noriaki Setoguchi
Noriaki Setoguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20040150354Abstract: Disclosed is a method for driving a plasma display panel in which a plurality of first electrodes and second electrodes are arranged parallel to each other, a plurality of third electrodes are arranged to cross the first and second electrodes, and discharge cells defined with areas in which the electrodes cross mutually are arranged in the form of a matrix. According to the driving method, a reset period is a period during which the distribution of wall charges in the plurality of discharge cells is uniformed. An addressing period is a period during which wall charges are produced in the discharge cells according to display data. A sustain discharge period is a period during which sustain discharge is induced in the discharge cells in which wall charges are produced during the addressing period.Type: ApplicationFiled: December 31, 2003Publication date: August 5, 2004Applicant: FUJITSU LIMITEDInventors: Noriaki Setoguchi, Shigeharu Asao, Yoshikazu Kanazawa
-
Patent number: 6707436Abstract: Disclosed is a method for driving a plasma display panel in which a plurality of first electrodes and second electrodes are arranged parallel to each other, a plurality of third electrodes are arranged to cross the first and second electrodes, and discharge cells defined with areas in which the electrodes cross mutually are arranged in the form of a matrix. According to the driving method, a reset period is a period during which the distribution of wall charges in the plurality of discharge cells is uniformed. An addressing period is a period during which wall charges are produced in the discharge cells according to display data. A sustain discharge period is a period during which sustain discharge is induced in the discharge cells in which wall charges are produced during the addressing period.Type: GrantFiled: June 17, 1999Date of Patent: March 16, 2004Assignee: Fujitsu LimitedInventors: Noriaki Setoguchi, Shigeharu Asao, Yoshikazu Kanazawa
-
Publication number: 20040012546Abstract: A driving circuit of a plasma display panel is provided in which a display cell including a first electrode and a second electrode is selected to light up, for applying a first voltage Vs1 to the first electrode and a second voltage Vs2 to the second electrode adjacent to the first electrode to cause a sustain discharge between the first and second electrodes. The driving circuit generates a sustain discharge voltage such that, during the sustain discharge between the first and second electrodes, an applied voltage Vc to a third electrode adjacent to the first electrode opposite to the second electrode falls within a range Vs2≦Vc<Vs1, and, in this case, when a display cell including the third electrode is selected to light up, the polarity of a wall charge formed on the third electrode becomes positive.Type: ApplicationFiled: May 19, 2003Publication date: January 22, 2004Applicant: FUJITSU HITACHI PLASMA DISPLAY LIMITEDInventors: Akihiro Takagi, Takashi Shiizaki, Takayuki Shimizu, Noriaki Setoguchi, Hitoshi Hirakawa, Tomokatsu Kishi
-
Patent number: 6667579Abstract: In a plasma display panel with stable performance and high contrast, even when a voltage that changes gradually as time goes by is applied between the first and the second electrodes so that a discharge is caused to occur only in a cell that was lit in the preceding subfield, the neighboring cell write, in which the wall charges that remain on one side of the different display lines contiguous to the cell that was lit in the preceding cell are eliminated, is provided before or after the write period.Type: GrantFiled: August 31, 2001Date of Patent: December 23, 2003Assignee: Fujitsu Hitachi Plasma Display LimitedInventors: Yoshikazu Kanazawa, Noriaki Setoguchi
-
Publication number: 20030184226Abstract: A plasma display panel including a first substrate carrying thereon a plurality of strip-shaped ribs arranged parallel to each other, a fluorescent material applied between adjacent ribs and a plurality of address electrodes arranged parallel to the ribs and a second substrate being arranged to oppose to the first substrate and carrying thereon a plurality of sustain electrodes arranged in a direction crossing the address electrodes, wherein each of the address electrodes between adjacent ribs includes a plurality of branch electrodes which are diverged through almost the whole length of the ribs.Type: ApplicationFiled: March 20, 2003Publication date: October 2, 2003Applicant: Fujitsu Hitachi Plasma Display LimitedInventors: Noriaki Setoguchi, Seiki Kurogi
-
Publication number: 20030184224Abstract: A plasma display panel includes a first substrate and a second substrate opposed to each other, a plurality of sustain electrodes arranged parallel to each other on an inside surface of the first substrate, a plurality of ribs arranged orthogonally to the sustain electrodes on an inside surface of the second substrate, and elongated address electrodes each arranged between adjacent ribs, wherein adjacent sustain electrodes have a pair of protrusions projected in a direction approaching each other and one of the pairs of protrusions of two adjacent sustain electrode pairs is displaced from the other pair of protrusions along the sustain electrodes between the ribs.Type: ApplicationFiled: March 17, 2003Publication date: October 2, 2003Applicant: Fujitsu Hitachi Plasma Display LimitedInventor: Noriaki Setoguchi
-
Patent number: 6608609Abstract: A method for driving a plasma display panel constituted by a group of cells each having a memory function, comprising arranging first and second electrodes in parallel with one another for each display line on a first substrate, arranging third electrodes on a second substrate opposing the first substrate in such a manner as to cross the first and second electrodes, and repeating light emission display by utilizing a selective address discharge for generating wall charges in cells selected by either one of the first and second electrodes and by the third electrodes and a sustain discharge executed repeatedly for the cells in which the wall charges are generated, is disclosed in which a pulse having a higher voltage than a priming pulse for executing a priming discharge after the activation of the cells is applied between the first and second electrodes only at the time of activation of the cells.Type: GrantFiled: May 12, 1999Date of Patent: August 19, 2003Assignee: Fujitsu LimitedInventors: Noriaki Setoguchi, Shigeharu Asao, Yoshikazu Kanazawa
-
Patent number: 6593693Abstract: A plasma display panel having a high power efficiency by reducing parasitic capacitances comprises first and second substrates disposed facing each other, a plurality of address lines formed on the first substrate and extending along a first direction and a plurality of X and Y electrodes formed on the second substrate and extending along a second direction crossing the first direction. A first dielectric layer covers the X and Y electrodes formed on the second substrate, the first dielectric layer having a dielectric constant higher than a dielectric constant of the second substrate, and a trench formed at least through the first dielectric layer in an area between two adjacent X and Y electrodes, the trench extending along the second direction.Type: GrantFiled: June 20, 2000Date of Patent: July 15, 2003Assignee: Fujitsu LimitedInventors: Akihiro Takagi, Tadatsugu Hirose, Shigeki Kameyama, Tomokatsu Kishi, Noriaki Setoguchi
-
Publication number: 20030001801Abstract: In a plasma display, a plurality of first display electrodes and a plurality of second electrodes are arranged in parallel with one another and in which a plurality of addressing electrodes are arranged to intersect the first and the second display electrodes. When a sustaining discharge is generated between the first and the second display electrode by applying an anode potential to one of the first and the second display electrode and a cathode potential to the other thereof, a potential lower than the anode potential and higher than the cathode potential is applied to the first and the second display electrode adjacent to the first and the second display electrode between which the sustaining discharge is generated.Type: ApplicationFiled: January 3, 2002Publication date: January 2, 2003Applicant: FUJITSU HITACHI PLASMA DISPLAY LIMITEDInventors: Noriaki Setoguchi, Tomokatsu Kishi
-
Patent number: 6489939Abstract: A method for driving an interlace system plasma display panel comprising applying a pulse higher than a discharge start voltage at the end of a sustain discharge period for a period in which only a cell that has executed a sustain discharge and cells adjacent to the former cell start discharge, executing an erase discharge of the cell that has executed the sustain discharge, and at times, the cells adjacent to the former cell, and when a given field is switched over to another field, executing a similar discharge, i.e., the whole surface write operation and a self-erase discharge, of the cell that has executed display before the switch-over of the given field before the whole surface write operation and the self-erase discharge are effected in the cell that is to execute display after the switch-over of the given field. This driving method applies a pulse having an opposite polarity of the polarity of the whole surface write pulse for a period longer than the pulse width of the sustain discharge pulse.Type: GrantFiled: March 3, 1999Date of Patent: December 3, 2002Assignee: Fujitsu LimitedInventors: Shigeharu Asao, Noriaki Setoguchi, Yoshikazu Kanazawa
-
Patent number: 6483251Abstract: The method of driving the plasma display, in which a discharge for the address action is caused to occur without fail even if the voltage of the address pulse is low and its width is narrow, has been disclosed. A display frame comprises plural subframes, the gradation display is attained by combining the lit subframes, each subframe comprises the reset period, the address period, and the sustain period, the reset voltage difference applied between the first electrode and the second electrode in the reset period and the address voltage difference applied between the first electrode and the second electrode in the address period can be set arbitrarily for each subframe, and the display frame includes plural subframes in which at least the reset voltage difference or the address voltage difference is different.Type: GrantFiled: August 15, 2001Date of Patent: November 19, 2002Assignee: Fujitsu Hitachi Plasma Display LimitedInventors: Noriaki Setoguchi, Takahiro Takamori, Tomokatsu Kishi
-
Publication number: 20020167466Abstract: Disclosed is a method for driving a plasma display panel in which a plurality of first electrodes and second electrodes are arranged parallel to each other, a plurality of third electrodes are arranged to cross the first and second electrodes, and discharge cells defined with areas in which the electrodes cross mutually are arranged in the form of a matrix. According to the driving method, a reset period is a period during which the distribution of wall charges in the plurality of discharge cells is uniformed. An addressing period is a period during which wall charges are produced in the discharge cells according to display data. A sustain discharge period is a period during which sustain discharge is induced in the discharge cells in which wall charges are produced during the addressing period.Type: ApplicationFiled: June 17, 1999Publication date: November 14, 2002Inventors: NORIAKI SETOGUCHI, SHIGEHARU ASAO
-
Publication number: 20020097200Abstract: A plasma display includes address electrodes for scanning and addressing display cells, and scan electrodes for establishing an address discharge between the address electrodes and the scan electrodes by addressing. The display also includes common electrodes for establishing a sustain discharge between the scan electrodes and the common electrodes to display an image at the display cells, and a scan driver for supplying a voltage to the scan electrodes so as to scan display cells upon addressing during divided periods. Upon addressing, the scan driver varies the potential of a scan electrode adjacent to the scan electrode that corresponds to the addressed address electrode.Type: ApplicationFiled: October 26, 2001Publication date: July 25, 2002Applicant: FUJITSU HITACHI PLASMA DISPLAY LIMITEDInventors: Noriaki Setoguchi, Takahiro Takamori, Eiji Ito, Tomokatsu Kishi
-
Publication number: 20020097003Abstract: After a sustain discharge period, a voltage twice a sustain pulse is applied to one of sustain discharge electrodes to form, on an address electrode, wall charges capable of self-erase discharge between an address electrode and the sustain discharge electrode by an address pulse, and the address pulse is applied to the address electrode to perform self-erase discharge between the address electrode and the sustain discharge electrode, thereby removing the wall charges formed on the address electrode. With this arrangement, a cell to be turned on in accordance with display data can be accurately selected in an address period without forming any wall charges on the address electrode, and any degradation in drive margin or display quality of a plasma display device can be suppressed.Type: ApplicationFiled: November 13, 2001Publication date: July 25, 2002Applicant: FUJITSU HITACHI PLASMA DISPLAY LIMTEDInventors: Takahiro Takamori, Noriaki Setoguchi, Eiji Ito, Tomokatsu Kishi
-
Publication number: 20020053882Abstract: A plasma display panel with stable performance and high contrast has been disclosed. In this panel, even when a voltage that changes gradually as time goes by is applied between the first and the second electrodes so that a discharge is caused to occur only in a cell that was lit in the preceding subfield, the neighboring cell write, in which the wall charges that remain on one side of the different display lines contiguous to the cell that was lit in the preceding cell are eliminated, is provided before or after the write period.Type: ApplicationFiled: August 31, 2001Publication date: May 9, 2002Applicant: FUJITSU HITACHI PLASMA DISPLAY LIMITEDInventors: Yoshikazu Kanazawa, Noriaki Setoguchi
-
Publication number: 20020050960Abstract: A plasma display drive method, in which the address action is carried out in a short time without fail, has been disclosed. In the reset action, wall charges are left uniformly in the display cell, and the following address action comprises the selective action to select the OFF cell, the eliminative action to eliminate the wall charges in the OFF cell selected in the selective action, and the write action to form wall charges needed for the sustain action in the ON cell.Type: ApplicationFiled: August 21, 2001Publication date: May 2, 2002Applicant: FUJITSU HITACHI PLASMA DISPLAY LIMITEDInventors: Noriaki Setoguchi, Tomokatsu Kishi
-
Publication number: 20020047578Abstract: The plasma display apparatus, in which the light emission efficiency is improved, has been disclosed. The fourth electrodes, which extend in the same direction of the first electrodes (X electrode) and the second electrodes (Y electrodes) and are exposed into the discharge space, are provided between the first and the second electrodes where the sustaining discharge is carried out, and when the sustain action is carried out, the fixed voltage between the voltage applied to the first electrode and that applied to the second electrode is applied to the fourth electrode provided between the first and the second electrodes where the sustain action is carried out in order to make the electric field between the first and the second electrodes uniform.Type: ApplicationFiled: September 26, 2001Publication date: April 25, 2002Applicant: FUJITSU HITACHI PLASMA DISPLAY LIMITEDInventors: Tomokatsu Kishi, Yoshikazu Kanazawa, Eiji Ito, Takahiro Takamori, Noriaki Setoguchi
-
Publication number: 20020041161Abstract: The method of driving the plasma display, in which a discharge for the address action is caused to occur without fail even if the voltage of the address pulse is low and its width is narrow, has been disclosed. A display frame comprises plural subframes, the gradation display is attained by combining the lit subframes, each subframe comprises the reset period, the address period, and the sustain period, the reset voltage difference applied between the first electrode and the second electrode in the reset period and the address voltage difference applied between the first electrode and the second electrode in the address period can be set arbitrarily for each subframe, and the display frame includes plural subframes in which at least the reset voltage difference or the address voltage difference is different.Type: ApplicationFiled: August 15, 2001Publication date: April 11, 2002Applicant: FUJITSU HITACHI PLASMA DISPLAY LIMITEDInventors: Noriaki Setoguchi, Takahiro Takamori, Tomokatsu Kishi
-
Patent number: 6084558Abstract: Disclosed is a drive method that ensures normal display on a stable basis for a plasma display panel in which sustaining discharge pulses that are mutually out of phase are applied to adjoining slits in order to initiate sustaining discharge, and to thus specify display slits between an Y electrode and X electrodes across the Y electrode. A plasma display device has a display panel including first and second electrodes arranged in parallel with one another and third electrodes arranged to be orthogonal to the first and second electrodes. A slit coincident with a line formed by discharge cells is selected by applying a scanning pulse and addressing signal at an addressing step, and sustaining discharge is initiated in the selected slit at a sustaining discharge step. According to the drive method for the plasma display device, first and second slits are defined between a second electrode and first electrodes on one side and the other side of the second electrode.Type: GrantFiled: September 21, 1998Date of Patent: July 4, 2000Assignee: Fujitsu LimitedInventors: Noriaki Setoguchi, Shigeharu Asao, Yoshikazu Kanazawa