Patents by Inventor Norifumi Kamiya

Norifumi Kamiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210391945
    Abstract: A communication apparatus for forward error correction and detection using polar codes comprising a polar encoder that encodes an input vector to output a codeword using a generator matrix of polar code wherein the input vector is a cyclic redundancy check (CRC) codeword of an information block; a memory that stores a frozen set including frozen bit indices and a non-frozen set including non-frozen bit indices sorted in order of error probabilities; and a controller that is configured to take as input the CRC codeword where CRC bits appended to the end of information block and interleave the CRC codeword using at least one of a first interleaver and second interleaver before feeding the CRC codeword to polar encoder such that the first interleaver places at least one CRC bit earlier than its original position in the CRC codeword and a second interleaver selects at least one bit from the CRC codeword whose corresponding index in a parity check matrix of the CRC code has the highest column weight and puts it in
    Type: Application
    Filed: October 10, 2018
    Publication date: December 16, 2021
    Applicant: NEC Corporation
    Inventors: Prakash CHAKI, Norifumi KAMIYA
  • Patent number: 11177834
    Abstract: A communication device includes: an encoder that encodes an input vector to output a codeword using a generator matrix of polar code; a memory that stores a frozen set including frozen bit indices and a non-frozen set including non-frozen bit indices; and a controller that is configured to: a) select at least one check bit index from the frozen set in descending order of row weights of the generator matrix and in descending order of index reliabilities of the input vector; b) select at least one non-frozen bit index from the non-frozen set to compute at least one check bit from at least one bit of information bits at the at least one non-frozen bit index; and c) put the at least one check bit at the at least one check bit index.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: November 16, 2021
    Assignee: NEC CORPORATION
    Inventors: Prakash Chaki, Norifumi Kamiya
  • Patent number: 11165438
    Abstract: [Problem] Encoding and decoding techniques capable of speeding up an error-correction decoding process utilizing channel polarization are provided. [Solution] In an encoding device, the information bit sequence is input on division for each designated bit length; error-correction encoding is performed on an information block of the designated bit length to generate L M-bit codes, each M-bit code having a predetermined bit length M; the L M-bit codes are converted into M L-bit blocks each having a predetermined bit length of L; the M L-bit blocks are Polar-converted to M L-bit codes, each L-bit code having a bit length of L, through channel polarization processing; and division of the information bit sequence is determined based on channel polarization information.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: November 2, 2021
    Assignee: NEC CORPORATION
    Inventor: Norifumi Kamiya
  • Publication number: 20210320707
    Abstract: An apparatus performs a discrete Fourier transform process on M×N received signal components included in a received signal, by a unit of N received signal components; and estimates an estimated signal containing M×N estimated signal components, which are estimated values of M×N transmission signal components, on the basis of the received signal on which the discrete Fourier transform process is performed. When the estimated signal xe is newly estimated, the apparatus performs an exclusion operation of excluding an estimated value xe(k) of the M transmission signal components that constitute a k-th transmission signal group from the estimated signal xe newly estimated, and updates the estimated value xe? based on an intermediate signal xt(k) obtained by the exclusion operation and the received signal, thereby re-estimating the estimated signal xe.
    Type: Application
    Filed: April 1, 2021
    Publication date: October 14, 2021
    Applicant: NEC Corporation
    Inventor: Norifumi KAMIYA
  • Publication number: 20210250052
    Abstract: A decoding apparatus (10) includes a multi-input branch metric calculation unit (11) configured to calculate, by using a branch label corresponding to a path extending toward a state S at a time point N in a trellis diagram and a plurality of reception signal sequences, a branch metric in the state S, a path metric calculation unit (12) configured to calculate a path metric in the state S at the time point N, and a surviving path list memory (13) configured to store path labels corresponding to L path metrics among a plurality of calculated path metrics. The path metric calculation unit (12) generates a path label in the state S at the time point N by combining the branch label with a path label in each of the states at the time point N?1 and the surviving path list memory (13) outputs path labels corresponding to L path metrics.
    Type: Application
    Filed: June 8, 2018
    Publication date: August 12, 2021
    Applicant: NEC CORPORATION
    Inventor: Norifumi KAMIYA
  • Publication number: 20200373945
    Abstract: A communication apparatus includes: an encoder that encodes an input vector to output a codeword of polar code; a memory that stores a reliability-ordered sequence of indices of the input vector and a set of indices for rate-matching; a controller that is configured to: select a frozen set of indices based on at least one of a universal rate-matching scheme and the reliability-ordered sequence stored in the memory such that the reliability-ordered sequence is generated without considering the rate-matching scheme; construct the input vector by setting the frozen set to a frozen bit and a non-frozen set to information bits; and skip codebits of the codeword outputted by the encoder from transmission, the codebits corresponding respectively to the set of indices for rate-matching.
    Type: Application
    Filed: August 10, 2017
    Publication date: November 26, 2020
    Applicant: NEC CORPORATION
    Inventors: Prakash CHAKI, Norifumi KAMIYA
  • Publication number: 20200321982
    Abstract: [Problem] Encoding and decoding techniques capable of speeding up an error-correction decoding process utilizing channel polarization are provided. [Solution] In an encoding device, the information bit sequence is input on division for each designated bit length; error-correction encoding is performed on an information block of the designated bit length to generate L M-bit codes, each M-bit code having a predetermined bit length M; the L M-bit codes are converted into M L-bit blocks each having a predetermined bit length of L; the M L-bit blocks are Polar-converted to M L-bit codes, each L-bit code having a bit length of L, through channel polarization processing; and division of the information bit sequence is determined based on channel polarization information.
    Type: Application
    Filed: December 27, 2017
    Publication date: October 8, 2020
    Applicant: NEC Corporation
    Inventor: Norifumi KAMIYA
  • Patent number: 10763973
    Abstract: A phase noise compensation apparatus is used for a demodulation apparatus for demodulating a transmission signal modulated by a modulation scheme that uses phase information for data identification. A phase detector detects a phase error of a reception pilot symbol sequence included in a reception symbol sequence. A first filter refers to the phase error detected in a time series manner and sequentially estimates first phase noise components. A second filter refers to the phase error detected in a reverse time series manner and sequentially estimates second phase noise components. The synthesis processing unit estimates a phase noise component of a reception symbol based on an estimated value of the first phase noise component, an estimated value of the second phase noise component, and the phase error. The phase rotator rotates a phase of the reception symbol based on the estimated phase noise component of the reception symbol.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: September 1, 2020
    Assignee: NEC CORPORATION
    Inventors: Norifumi Kamiya, Eisaku Sasaki
  • Patent number: 10715375
    Abstract: A modulation device includes a mapping circuit configured to map information bits to signal points on a plurality of concentric rings, when a signal space arrangement in which the number of signal points on all of the plurality of rings is the same is used as a basis, reduce the number of signal points on an innermost ring or a plurality of rings from inner to outer rings from among the plurality of rings, generate a new ring outside the signal space arrangement used as the basis, and arrange, on the generated ring, signal points which achieve the same frequency utilization efficiency as that of the signal space arrangement used as the basis.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: July 14, 2020
    Assignee: NEC CORPORATION
    Inventors: Norifumi Kamiya, Mamoru Sawahashi
  • Publication number: 20200201712
    Abstract: [Problem] A novel method and apparatus is provided, which are capable of avoiding a decrease in detection accuracy and a large increase in the amount of calculation, and capable of generating redundant bits allowing detection of errors using part of information bits. [Solution] A redundant bit generating device that generates redundant bits for error detection, that are added to a block of information bits, includes: a redundant bit calculation function (30) that generates a predetermined number (r) of redundant bits from the information bits according to a CRC polynomial (32); and a bit interleaving function (31) that dispersedly arranges the predetermined number of redundant bits within the information bits using a permutation pattern (33) determined based on the CRC polynomial (32).
    Type: Application
    Filed: August 9, 2017
    Publication date: June 25, 2020
    Applicant: NEC Corporation
    Inventors: Norifumi KAMIYA, Prakash CHAKI
  • Publication number: 20200092155
    Abstract: A modulation device includes a mapping circuit configured to map information bits to signal points on a plurality of concentric rings, when a signal space arrangement in which the number of signal points on all of the plurality of rings is the same is used as a basis, reduce the number of signal points on an innermost ring or a plurality of rings from inner to outer rings from among the plurality of rings, generate a new ring outside the signal space arrangement used as the basis, and arrange, on the generated ring, signal points which achieve the same frequency utilization efficiency as that of the signal space arrangement used as the basis.
    Type: Application
    Filed: December 21, 2016
    Publication date: March 19, 2020
    Applicant: NEC CORPORATION
    Inventors: Norifumi KAMIYA, Mamoru SAWAHASHI
  • Publication number: 20200052719
    Abstract: A communication device includes: an encoder that encodes an input vector to output a codeword using a generator matrix of polar code; a memory that stores a frozen set including frozen bit indices and a non-frozen set including non-frozen bit indices; and a controller that is configured to: a) select at least one check bit index from the frozen set in descending order of row weights of the generator matrix and in descending order of index reliabilities of the input vector; b) select at least one non-frozen bit index from the non-frozen set to compute at least one check bit from at least one bit of information bits at the at least one non-frozen bit index; and c) put the at least one check bit at the at least one check bit index.
    Type: Application
    Filed: March 30, 2017
    Publication date: February 13, 2020
    Applicant: NEC Corporation
    Inventors: Prakash CHAKI, Norifumi KAMIYA
  • Patent number: 10523283
    Abstract: A LOS-MIMO demodulation apparatus comprises a plurality of receive antennas that receive data; a phase noise estimation part that calculates, from each signal received, first phase noise information and second phase noise information relating to phase noise occurring at transmit antennas and the receive antennas; a first correction part that corrects a phase of each signal received by the plurality of receive antennas according to the first phase noise information; a frequency domain equalization part that performs frequency domain equalization processing compensating for distortion due to interference from each signal received; a second correction part that corrects, according to the second phase noise information, a phase of each signal obtained by returning the signals, on which the frequency domain equalization processing has been performed, to the time domain by performing an inverse discrete Fourier transform; and a decoding processing part that performs decoding processing on the corrected data.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 31, 2019
    Assignee: NEC CORPORATION
    Inventor: Norifumi Kamiya
  • Publication number: 20190260398
    Abstract: A communication device includes: an encoder that encodes an input vector to output a codeword of Polar Code; a memory configured to store a frozen set of positions of frozen bits and a puncturing set of positions of punctured bits; and at least one processor configured to execute a set of instructions to: a) set the frozen set such that a punctured bit has a constant value; b) select the position of a punctured bit such that a minimum number of indices get frozen; c) freeze an index that has a highest decoding error probability among a plurality of indices selected according to the step b); d) repeat the steps b) and c) a predetermined number of times to obtain an array of indices; and e) perform a bit-reversal permutation of the array obtained in the step d) to generate the positions of the punctured bits in the puncturing set.
    Type: Application
    Filed: October 21, 2016
    Publication date: August 22, 2019
    Applicant: NEC Corporation
    Inventors: Prakash CHAKI, Norifumi KAMIYA
  • Publication number: 20190207683
    Abstract: A phase noise compensation apparatus is used for a demodulation apparatus for demodulating a transmission signal modulated by a modulation scheme that uses phase information for data identification. A phase detector detects a phase error of a reception pilot symbol sequence included in a reception symbol sequence. A first filter refers to the phase error detected in a time series manner and sequentially estimates first phase noise components. A second filter refers to the phase error detected in a reverse time series manner and sequentially estimates second phase noise components. The synthesis processing unit estimates a phase noise component of a reception symbol based on an estimated value of the first phase noise component, an estimated value of the second phase noise component, and the phase error. The phase rotator rotates a phase of the reception symbol based on the estimated phase noise component of the reception symbol.
    Type: Application
    Filed: May 16, 2017
    Publication date: July 4, 2019
    Applicant: NEC Corporation
    Inventors: Norifumi KAMIYA, Eisaku SASAKI
  • Publication number: 20190020384
    Abstract: A LOS-MIMO demodulation apparatus comprises a plurality of receive antennas that receive data; a phase noise estimation part that calculates, from each signal received, first phase noise information and second phase noise information relating to phase noise occurring at transmit antennas and the receive antennas; a first correction part that corrects a phase of each signal received by the plurality of receive antennas according to the first phase noise information; a frequency domain equalization part that performs frequency domain equalization processing compensating for distortion due to interference from each signal received; a second correction part that corrects, according to the second phase noise information, a phase of each signal obtained by returning the signals, on which the frequency domain equalization processing has been performed, to the time domain by performing an inverse discrete Fourier transform; and a decoding processing part that performs decoding processing on the corrected data.
    Type: Application
    Filed: April 18, 2017
    Publication date: January 17, 2019
    Applicant: NEC Corporation
    Inventor: Norifumi KAMIYA
  • Patent number: 10009133
    Abstract: A MIMO demodulating apparatus includes: a phase difference corrector that compensates for a phase shift by utilizing the phase difference between received signals to output phase corrected signals; an interference compensator that receives the phase corrected signals as input and, by means of adaptive control, performs elimination of interference and separation and extraction of a desired signal; a phase noise compensator to compensate for phase error remaining in the desired signal; a signal determiner that determines transmitted data from the output signal of the phase noise compensator to output the transmitted data and outputs an error signal; and an error signal phase rotator that subjects the error signal to a phase rotating process in accordance with the phase error compensation amount to perform adaptive control.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: June 26, 2018
    Assignee: NEC CORPORATION
    Inventor: Norifumi Kamiya
  • Patent number: 9876668
    Abstract: To enable a large-capacity, high-quality data communication that is excellent in bit error rate characteristic even in an adverse noise environment mainly caused by phase noises or thermal noises. [Solution] Included are: a first phase error detection filter that generates, on the basis of a forward sequence of received symbols, a first phase difference value and a first phase error estimated value; a second phase error detection filter that generates, on the basis of a backward sequence of received symbols, a second phase difference value and a second phase error estimated value; a phase error combination means that generates a third phase error estimated value on the basis of the first and second phase error estimated values and one of the first and second phase difference values; and a phase error compensation means that compensates the phase error of the received symbols in accordance with the third phase error estimated value.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: January 23, 2018
    Assignee: NEC Corporation
    Inventors: Norifumi Kamiya, Eisaku Sasaki
  • Publication number: 20180019835
    Abstract: A MIMO demodulating apparatus includes: a phase difference corrector that compensates for a phase shift by utilizing the phase difference between received signals to output phase corrected signals; an interference compensator that receives the phase corrected signals as input and, by means of adaptive control, performs elimination of interference and separation and extraction of a desired signal; a phase noise compensator to compensate for phase error remaining in the desired signal; a signal determiner that determines transmitted data from the output signal of the phase noise compensator to output the transmitted data and outputs an error signal; and an error signal phase rotator that subjects the error signal to a phase rotating process in accordance with the phase error compensation amount to perform adaptive control.
    Type: Application
    Filed: December 15, 2015
    Publication date: January 18, 2018
    Applicant: NEC CORPORATION
    Inventor: Norifumi KAMIYA
  • Publication number: 20160330064
    Abstract: To enable a large-capacity, high-quality data communication that is excellent in bit error rate characteristic even in an adverse noise environment mainly caused by phase noises or thermal noises. [Solution] Included are: a first phase error detection filter that generates, on the basis of a forward sequence of received symbols, a first phase difference value and a first phase error estimated value; a second phase error detection filter that generates, on the basis of a backward sequence of received symbols, a second phase difference value and a second phase error estimated value; a phase error combination means that generates a third phase error estimated value on the basis of the first and second phase error estimated values and one of the first and second phase difference values; and a phase error compensation means that compensates the phase error of the received symbols in accordance with the third phase error estimated value.
    Type: Application
    Filed: January 15, 2015
    Publication date: November 10, 2016
    Applicant: NEC Corporation
    Inventors: Norifumi KAMIYA, Eisaku SASAKI