Patents by Inventor Norifumi Kamiya
Norifumi Kamiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9136979Abstract: The present invention provides a carrier wave reproduction device in which bit-error characteristics are improved without decreasing transmission capacity.Type: GrantFiled: April 23, 2013Date of Patent: September 15, 2015Assignee: NEC CORPORATIONInventors: Norifumi Kamiya, Eisaku Sasaki
-
Publication number: 20150085960Abstract: The present invention provides a carrier wave reproduction device in which bit-error characteristics are improved without decreasing transmission capacity.Type: ApplicationFiled: April 23, 2013Publication date: March 26, 2015Applicant: NEC CORPORATIONInventors: Norifumi Kamiya, Eisaku Sasaki
-
Patent number: 8958492Abstract: By using circularly-arranged signal points obtained by rearranging a part of signal points arranged in a rectangular shape or a cross shape, average signal power and peak signal energy are reduced to improve nonlinear distortion characteristics. Provided is a bit mapping method in which an average value of a Hamming distance in terms of a specified lower bit portion between adjacent signal points is small, and a Euclidean distance between signal points at which the lower bit portions assigned thereto coincide with each other becomes maximum. By applying error correction code only to the lower bit portion, a data transmission method excellent in bit error rate characteristics is provided while suppressing a band expansion rate.Type: GrantFiled: December 1, 2010Date of Patent: February 17, 2015Assignee: NEC CorporationInventors: Norifumi Kamiya, Eisaku Sasaki
-
Patent number: 8910014Abstract: A coding device includes: an inspection matrix generating module that generates a block inspection matrix; and a coding module that generates and outputs a code word from an input message by the inspection matrix. The inspection matrix generating module includes: a degree-allocation unit that prescribes function values of the block inspection matrix by the coefficients of a self-reciprocal polynomial expression; a weight distribution determination unit that prescribes the number of components that are non-zero matrices among the components of each block of the block inspection matrix using a mask pattern; a first degree-altering unit that considers the sum of the components of the k_r-th row block of the block inspection matrix as a cyclic permutation matrix; and a second degree-altering unit that prescribes the row-block number of components that are non-zero matrices among the components of each row block excluding said k_r-th row block of the clock inspection matrix.Type: GrantFiled: April 19, 2011Date of Patent: December 9, 2014Assignee: NEC CorporationInventor: Norifumi Kamiya
-
Patent number: 8713398Abstract: Disclosed are an encoding apparatus for a quasi-cyclic low-density parity check code for calculating r×m-bit redundant data for information data of length k×m bits (k, m and r are positive integers), and a cyclic addition apparatus including a k×m-bit shift register and exclusive OR. With information data of a length of k×m×L bits (L?k), a length of (r×m×(L+1)+k×m) bits is calculated as redundant data by adding redundant data of a length of r×m×L bits calculated using the encoding apparatus L times, k×m-bit data calculated by inputting the information data of a length of k×m×L bits to the cyclic addition apparatus, and r×m-bit redundant data calculated by inputting the k×m-bit data to the encoding apparatus.Type: GrantFiled: March 22, 2012Date of Patent: April 29, 2014Assignee: NEC CorporationInventor: Norifumi Kamiya
-
Patent number: 8667376Abstract: A decoding device comprises two check node processing devices of feedback shift register type, each of which node processing includes a plurality of registers and a plurality of comparator circuits. A multiplexer and a demultiplexer switch between the two check node processing devices, and a memory holds the two sorts of data. The comparator circuits are interposed between registers of the check node processing device.Type: GrantFiled: November 6, 2009Date of Patent: March 4, 2014Assignee: NEC CorporationInventor: Norifumi Kamiya
-
Patent number: 8627172Abstract: Provided is an encoding apparatus wherein a transmission data sequence is divided into L short sequences, each of which is then encoded by use of an m-stage pseudo-cyclic low-density parity check encoding system. Each of the L encoded sequences is further divided into shorter sequences, the number of which is identical to the number m of the stages of the pseudo-cyclic codes and each of which has a length m. The shorter sequences are rearranged in order by a replacing module, thereafter encoded, by use of the m-stage pseudo-cyclic low-density parity check encoding system, and outputted. Accordingly, a decoding apparatus with a simple structure where node processing circuits (e.g., minimum-value calculating circuits), the number of which is p that is a submultiple of the number m of the foregoing stages, are provided, can be employed to efficiently decode the codes having a large frame length and a large encoding gain.Type: GrantFiled: December 11, 2009Date of Patent: January 7, 2014Assignee: NEC CorporationInventor: Norifumi Kamiya
-
Publication number: 20130179757Abstract: Disclosed are an encoding apparatus for a quasi-cyclic low-density parity check code for calculating r×m-bit redundant data for information data of length k×m bits (k, m and r are positive integers), and a cyclic addition apparatus including a k×m-bit shift register and exclusive OR. With information data of a length of k×m×L bits (L?k), a length of (r×m×(L+1)+k×m) bits is calculated as redundant data by adding redundant data of a length of r×m×L bits calculated using the encoding apparatus L times, k×m-bit data calculated by inputting the information data of a length of k×m×L bits to the cyclic addition apparatus, and r×m-bit redundant data calculated by inputting the k×m-bit data to the encoding apparatus.Type: ApplicationFiled: March 22, 2012Publication date: July 11, 2013Applicant: NEC CORPORATIONInventor: Norifumi Kamiya
-
Patent number: 8429486Abstract: A data converting means generates first interim data held in one-to-one correspondence to columns vectors from data stored in a first storage means and data stored in a second storage means. A check node processing means generates second interim data for updating the data stored in the first storage means based on the sum of the first interim data and received data. The data converting means updates the data stored in the second storage means using the first interim data, and updates the data stored in the first storage means using the second interim data generated by the check node processing means. Decoded data are generated by a process carried out by the data converting means and the check node processing means.Type: GrantFiled: October 28, 2008Date of Patent: April 23, 2013Assignee: NEC CorporationInventor: Norifumi Kamiya
-
Publication number: 20130031446Abstract: A coding device includes: an inspection matrix generating module that generates a block inspection matrix; and a coding module that generates and outputs a code word from an input message by the inspection matrix. The inspection matrix generating module includes: a degree-allocation unit that prescribes function values of the block inspection matrix by the coefficients of a self-reciprocal polynomial expression; a weight distribution determination unit that prescribes the number of components that are non-zero matrices among the components of each block of the block inspection matrix using a mask pattern; a first degree-altering unit that considers the sum of the components of the k_r-th row block of the block inspection matrix as a cyclic permutation matrix; and a second degree-altering unit that prescribes the row-block number of components that are non-zero matrices among the components of each row block excluding said k_r-th row block of the clock inspection matrix.Type: ApplicationFiled: April 19, 2011Publication date: January 31, 2013Applicant: NEC CORPORATIONInventor: Norifumi Kamiya
-
Patent number: 8205142Abstract: An error correction coding method using a low-density parity-check code includes: dividing an information bit sequence to be processed for error correction coding, into (m?r) pieces of first blocks each comprising a bit sequence having a length n and r pieces of second blocks comprising respective bit sequences having lengths k1, k2, . . . , kr; a first arithmetic operation for performing polynomial multiplication on the (m?r) pieces of first blocks, and outputting r pieces of bit sequences having a length n; and a second arithmetic operation for performing a polynomial division and a polynomial multiplication on the r pieces of second blocks and r pieces of operation results of the first arithmetic operation, and outputting a bit sequence including redundant bit sequences having respective lengths n?k1, n?k2, . . . , n?kr.Type: GrantFiled: April 25, 2007Date of Patent: June 19, 2012Assignee: NEC CorporationInventor: Norifumi Kamiya
-
Publication number: 20120089884Abstract: Provided is an encoding apparatus wherein a transmission data sequence is divided into L short sequences, each of which is then encoded by use of an m-stage pseudo-cyclic low-density parity check encoding system. Each of the L encoded sequences is further divided into shorter sequences, the number of which is identical to the number m of the stages of the pseudo-cyclic codes and each of which has a length m. The shorter sequences are rearranged in order by a replacing module, thereafter encoded, by use of the m-stage pseudo-cyclic low-density parity check encoding system, and outputted. Accordingly, a decoding apparatus with a simple structure where node processing circuits (e.g., minimum-value calculating circuits), the number of which is p that is a submultiple of the number m of the foregoing stages, are provided, can be employed to efficiently decode the codes having a large frame length and a large encoding gain.Type: ApplicationFiled: December 11, 2009Publication date: April 12, 2012Applicant: NEC CorporationInventor: Norifumi Kamiya
-
Patent number: 8074142Abstract: A decoding apparatus for low density parity check codes includes a variable-to-check message generator and a check-to-variable message generator. The variable-to-check message generator includes a variable-to-check processing unit block, provided with an adder, and which is arranged between registers corresponding to locations of ‘1’s in a check matrix. The check-to-variable message generator includes a check-to-variable processing unit block, provided with a comparator, between registers corresponding to locations of ‘1’s in the check matrix. The decoding apparatus for low density parity check codes is simple in configuration and is able to perform high speed processing without using RAMs without the necessity of performing complex control operations.Type: GrantFiled: September 21, 2006Date of Patent: December 6, 2011Assignee: NEC CorporationInventor: Norifumi Kamiya
-
Publication number: 20110219286Abstract: A decoding device comprises two check node processing devices of feedback shift register type, each of which node processing includes a plurality of registers and a plurality of comparator circuits. A multiplexer and a demultiplexer switch between the two check node processing devices, and a memory holds the two sorts of data. The comparator circuits are interposed between registers of the check node processing device.Type: ApplicationFiled: November 6, 2009Publication date: September 8, 2011Inventor: Norifumi Kamiya
-
Patent number: 7979780Abstract: An error correction encoding apparatus wherein the apparatus structure is simple; an iterative decoding is used to achieve a decoding with a close-to-optimum precision; and a simple mathematical expression is used to perform an evaluation of the characteristic of an error floor area without using any computer experiments. In a polynomial multiplying block 1, (n?1)-th-order polynomial multiplying units (12-1 to 12-(m?1)) further divide an information bit string, which has been blocked for an error correction encoding, into (m?1) blocks having a length n and a single block having a length (n?r) (where m and n represent integers equal to or greater than two and where r represents an integer between 1 and n inclusive); receive blocks, which have the length n, of divided information bit strings; and output a series having the same length.Type: GrantFiled: November 29, 2005Date of Patent: July 12, 2011Assignee: NEC CorporationInventor: Norifumi Kamiya
-
Publication number: 20100251063Abstract: A data converting means generates first interim data held in one-to-one correspondence to columns vectors from data stored in a first storage means and data stored in a second storage means. A check node processing means generates second interim data for updating the data stored in the first storage means based on the sum of the first interim data and received data. The data converting means updates the data stored in the second storage means using the first interim data, and updates the data stored in the first storage means using the second interim data generated by the check node processing means. Decoded data are generated by a process carried out by the data converting means and the check node processing means.Type: ApplicationFiled: October 28, 2008Publication date: September 30, 2010Inventor: Norifumi Kamiya
-
Publication number: 20100153810Abstract: A decoding apparatus for low density parity check codes includes a variable-to-check message generator and a check-to-variable message generator. The variable-to-check message generator includes a variable-to-check processing unit block, provided with an adder, and which is arranged between registers corresponding to locations of ‘1’s in a check matrix. The check-to-variable message generator includes a check-to-variable processing unit block, provided with a comparator, between registers corresponding to locations of ‘1’s in the check matrix. The decoding apparatus for low density parity check codes is simple in configuration and is able to perform high speed processing without using RAMs without the necessity of performing complex control operations.Type: ApplicationFiled: September 21, 2006Publication date: June 17, 2010Applicant: NEC CORPORATIONInventor: Norifumi Kamiya
-
Publication number: 20090187810Abstract: An error correction coding method using a low-density parity-check code includes: dividing an information bit sequence to be processed for error correction coding, into (m?r) pieces of first blocks each comprising a bit sequence having a length n and r pieces of second blocks comprising respective bit sequences having lengths k1, k2, . . . , kr; a first arithmetic operation for performing polynomial multiplication on the (m?r) pieces of first blocks, and outputting r pieces of bit sequences having a length n; and a second arithmetic operation for performing a polynomial division and a polynomial multiplication on the r pieces of second blocks and r pieces of operation results of the first arithmetic operation, and outputting a bit sequence including redundant bit sequences having respective lengths n?k1, n?k2, . . . , n?kr.Type: ApplicationFiled: April 25, 2007Publication date: July 23, 2009Applicant: NEC CORPORATIONInventor: Norifumi Kamiya
-
Publication number: 20070300135Abstract: An error correction encoding apparatus wherein the apparatus structure is simple; an iterative decoding is used to achieve a decoding with a close-to-optimum precision; and a simple mathematical expression is used to perform an evaluation of the characteristic of an error floor area without using any computer experiments. In a polynomial multiplying block 1, (n?1)-th-order polynomial multiplying units (12-1 to 12-(m?1)) further divide an information bit string, which has been blocked for an error correction encoding, into (m?1) blocks having a length n and a single block having a length (n-r) (where m and n represent integers equal to or greater than two and where r represents an integer between 1 and n inclusive); receive blocks, which have the length n, of divided information bit strings; and output a series having the same length.Type: ApplicationFiled: November 29, 2005Publication date: December 27, 2007Applicant: NEC CORPORATIONInventor: Norifumi Kamiya