Abstract: Provided are an oxygen concentrator, a control method, and a control program capable of preventing a drop in pilot pressure supplied to a pilot type solenoid valve used in at least either of the supply flow path opening/closing unit or the exhaust flow path opening/closing unit. An oxygen concentrator capable of preventing a pressure drop in both cylinders in the pressure equalization step and, as a result, preventing a drop in pilot pressure supplied to a pilot type solenoid valve used in at least either of the supply flow path opening/closing unit or the exhaust flow path opening/closing unit, as well as a pressure drop in the adsorption cylinder, by starting pressurization in advance in the already depressurized adsorption cylinder before the pressure equalization step.

Abstract: Provided are an oxygen concentrator, a control method, and a control program capable of preventing an internal pressure drop of the concentrated oxygen gas tank in order to extract concentrated oxygen gas at a predetermined flow rate. An oxygen concentrator capable of preventing a pressure drop in both cylinders in the pressure equalization step and, as a result, preventing a drop in the internal pressure of a concentrated oxygen gas tank, by starting pressurization in advance in the already depressurized adsorption cylinder before the pressure equalization step.

Abstract: There is provided an information processing apparatus, an information processing method, a program, and an information processing system which make it possible to improve the safety of a time variant key. The information processing apparatus according to one aspect of the present technique receives a first random number and a second random number which are transmitted from another information processing apparatus, generates a third random number, generates a first time variant key by causing the second random number and the third random number to act on a first fixed key, encrypts the first random number by using the first time variant key, and transmits the encrypted first random number and the third random number to the another information processing apparatus. The present technique can be applied to an IC card mounted with an IC chip for performing non-contact communication.

Abstract: An information processing apparatus, an information processing method, and a program capable of improving convenience of a device in which a virtual machine is able to operate are provided. An information processing apparatus is provided that includes a processing unit having a function for controlling execution of processing regarding a virtual machine, in which a virtual machine program that operates the virtual machine is associated with condition information that includes information indicating a region of a recording medium and indicates a condition under which the virtual machine is operated, a code of the virtual machine program, and a first electronic signature generated on the basis of the condition information, and the processing unit controls the execution of the processing regarding the virtual machine on the basis of a confirmation result of the first electronic signature associated with the virtual machine program.

Abstract: According to one embodiment, in a nonvolatile memory, the determination unit determines whether a change process is executable or not. The change process is a process based on characteristics of the memory cell array when a first write process is performed. The change process changes at least one of a value of a write start voltage and an increase amount in a write voltage in a second write process. The second write process is a process where a write operation of writing data to upper pages of at least part of the plurality of nonvolatile memory cells and a verification operation are alternately repeated. The setting unit sets a maximum value for determining whether the second write process succeeds or fails to a first value when the change process is executable, and sets the maximum value to a second value when the change process is not executable.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells and stores initial setting data in the plurality of memory cells. The control circuit is configured to apply a first voltage to gates of the plurality of memory cells to read the initial setting data and, depending on that read result, apply a second voltage different from the first voltage to the gates of the plurality of memory cells to read the initial setting data.

Abstract: According to one embodiment, in a nonvolatile memory, the determination unit determines whether a change process is executable or not. The change process is a process based on characteristics of the memory cell array when a first write process is performed. The change process changes at least one of a value of a write start voltage and an increase amount in a write voltage in a second write process. The second write process is a process where a write operation of writing data to upper pages of at least part of the plurality of nonvolatile memory cells and a verification operation are alternately repeated. The setting unit sets a maximum value for determining whether the second write process succeeds or fails to a first value when the change process is executable, and sets the maximum value to a second value when the change process is not executable.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells and stores initial setting data in the plurality of memory cells. The control circuit is configured to apply a first voltage to gates of the plurality of memory cells to read the initial setting data and, depending on that read result, apply a second voltage different from the first voltage to the gates of the plurality of memory cells to read the initial setting data.

Abstract: A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

Abstract: A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

Abstract: A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a control circuit. The control circuit is configured to repeat an application of a write pulse and a verify read operation to a selected word line, perform a read operation from a selected memory cell after storing of program data is judged to be completed by a verify circuit, and output a status information indicating that a program operation has passed to a external controller when data read by a read operation and a program data match and the status information indicating that the program operation has failed to the external controller when both do not match. A data latch circuit continues to latch the program data even after the storing of the program data is judged to be completed by the verify circuit.

Abstract: According to one embodiment, a semiconductor storage device includes a first cell, a second cell, a bit line, a first buffer, a second buffer, and a controller. The bit line transfers the data to the first cell and the second cell. The first buffer holds write data to the first cell and the second cell. The second buffer holds read data from the first cell. The controller controls first writing and rewriting executed for the first cell and second writing executed for the second cell. The write data in the first buffer is updated each time a second write signal is given. The controller executes the first writing based on the write data held by the first buffer. The controller performs the second writing based on the write data updated in the first buffer. The controller executes the rewriting based on the read data held by the second buffer.

Abstract: A nonvolatile semiconductor memory device and a nonvolatile memory system having a unit which suppresses erroneous reading of a nonvolatile semiconductor memory device of a multi-level memory system are provided. In the nonvolatile semiconductor memory device and the nonvolatile memory system of the multi-level memory system, a first verify voltage is used when data is written before a packaging process, and the verify voltage is switched to a second verify voltage lower than the first verify voltage when data is written after the packaging process.

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a control circuit. The control circuit is configured to repeat an application of a write pulse and a verify read operation to a selected word line, perform a read operation from a selected memory cell after storing of program data is judged to be completed by a verify circuit, and output a status information indicating that a program operation has passed to a external controller when data read by a read operation and a program data match and the status information indicating that the program operation has failed to the external controller when both do not match. A data latch circuit continues to latch the program data even after the storing of the program data is judged to be completed by the verify circuit.

Abstract: There is provided a communication device including a change request reception unit for receiving a change request for temporarily changing an encryption type of the communication device transmitted from an information processing device, an encryption type change unit for temporarily changing the encryption type of the communication device on the basis of the change request received by the change request reception unit, and an authentication information transmission unit for transmitting authentication information for causing the information processing device to authenticate the communication device encrypted in the encryption type temporarily changed by the encryption type change unit to the information processing device.

Abstract: Provided are a packet forwarding apparatus, a communication system, a process rule update method that can accurately delete process rules used for packet forwarding and the like. The packet forwarding apparatus comprises: a process rule storage unit storing a process rule defining a process content for each flow; a packet process unit using a process rule matching a received packet among the process rules and processing a received packet; an end determination information extraction unit extracting information for checking a flow end from the received packet; and a flow end check unit deleting, when a flow end is checked based on the extracted information, a process rule corresponding to the flow.

Abstract: A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.

Abstract: A nonvolatile semiconductor memory device and a nonvolatile memory system having a unit which suppresses erroneous reading of a nonvolatile semiconductor memory device of a multi-level memory system are provided. In the nonvolatile semiconductor memory device and the nonvolatile memory system of the multi-level memory system, a first verify voltage is used when data is written before a packaging process, and the verify voltage is switched to a second verify voltage lower than the first verify voltage when data is written after the packaging process.

Abstract: A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.