Patents by Inventor Norihiro Fujita
Norihiro Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110038206Abstract: According to one embodiment, a semiconductor storage device includes a first cell, a second cell, a bit line, a first buffer, a second buffer, and a controller. The bit line transfers the data to the first cell and the second cell. The first buffer holds write data to the first cell and the second cell. The second buffer holds read data from the first cell. The controller controls first writing and rewriting executed for the first cell and second writing executed for the second cell. The write data in the first buffer is updated each time a second write signal is given. The controller executes the first writing based on the write data held by the first buffer. The controller performs the second writing based on the write data updated in the first buffer. The controller executes the rewriting based on the read data held by the second buffer.Type: ApplicationFiled: August 12, 2010Publication date: February 17, 2011Inventors: Norihiro FUJITA, Yasuyuki Fukuda
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Patent number: 7867344Abstract: A method is proved for hot pressing hot rolled steel sheet, cold rolled steel sheet, Al-based plated steel sheet or Zn-based plated steel sheet, where the hot pressed sheet can exhibit a strength of at least about 1200 Mpa, and my be prevented from exhibiting hydrogen embrittlement. The steel sheet may include between about 0.05 to 0.5 wt % C, and/or it may be plated with an Al-based or Zn-based plating material. The steel sheet may be heating to a temperature greater than an Ac3 temperature and not more than about 1100° C. before pressing. An atmosphere can be provided during heating which contains not more than about 6 vol % of hydrogen and a dew point of not more than about 10° C. The exemplary methods may be used to form high strength parts which may be used, e.g., in automobiles.Type: GrantFiled: July 15, 2005Date of Patent: January 11, 2011Assignee: Nippon Steel CorporationInventors: Kazuhisa Kusumi, Jun Maki, Masayuki Abe, Masahiro Ohgami, Norihiro Fujita, Shinya Nakajima
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Patent number: 7826268Abstract: A nonvolatile semiconductor memory, has a first wire; a second wire adjacent to the first wire; a third wire disposed next to the second wire such that the second wire is disposed between the first wire and the third wire; a power supply circuit for setting each of the wires at a predetermined potential; and a determining circuit for determining presence or absence of a short circuit between the wires.Type: GrantFiled: September 23, 2008Date of Patent: November 2, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Norihiro Fujita, Toshihiko Himeno, Hitoshi Shiga
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Publication number: 20100238727Abstract: A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.Type: ApplicationFiled: May 27, 2010Publication date: September 23, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Norihiro FUJITA, Hiroyuki Nagashima, Hiroshi Nakamura
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Patent number: 7755947Abstract: A semiconductor memory device including: a package; a first semiconductor chip provided in the package; a first nonvolatile memory provided on the first semiconductor chip; a second semiconductor chip provided in the package; a second nonvolatile memory provided on the second semiconductor chip; a system bus provided in the package, the system bus connecting the first and second nonvolatile memories; a plurality of data terminals exposed to outside of the package, the data terminals being connected to the first and second nonvolatile memories through the system bus; and an enable terminal exposed to the outside of the package, the enable terminal being connected to the first and second nonvolatile memories.Type: GrantFiled: December 19, 2008Date of Patent: July 13, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Norihiro Fujita, Hiroyuki Nagashima, Hiroshi Nakamura
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Publication number: 20100165744Abstract: A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.Type: ApplicationFiled: March 12, 2010Publication date: July 1, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mikio Ogawa, Norihiro Fujita, Hiroshi Nakamura
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Patent number: 7701777Abstract: A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.Type: GrantFiled: December 19, 2008Date of Patent: April 20, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Mikio Ogawa, Norihiro Fujita, Hiroshi Nakamura
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Publication number: 20090323432Abstract: A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.Type: ApplicationFiled: June 25, 2009Publication date: December 31, 2009Inventors: Takuya Futatsuyama, Toshiaki Edahiro, Norihiro Fujita, Fumitaka Arai, Tohru Maruyama, Masaki Kondo
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Patent number: 7577030Abstract: A memory cell array has a plurality of multi-value memory cells arranged therein that can store information of two bits or more in one memory cell as a different page. In each of the data registers, an acceptable number setting register, which temporarily retains data read from the memory cell array, stores multiple acceptable numbers of data states corresponding to each state of threshold voltages of each of the pages in the multi-value memory cells. A selector selects, from the multiple acceptable numbers of data states, an acceptable number of data states for data retained in each of the data registers corresponding to each page of the multi-value memory cells. A comparator compares the number of data states retained in each of the data registers with the acceptable number of data states selected by the selector.Type: GrantFiled: January 17, 2008Date of Patent: August 18, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Naoya Tokiwa, Norihiro Fujita
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Publication number: 20090109753Abstract: A semiconductor memory device including: a package; a first semiconductor chip provided in the package; a first nonvolatile memory provided on the first semiconductor chip; a second semiconductor chip provided in the package; a second nonvolatile memory provided on the second semiconductor chip; a system bus provided in the package, the system bus connecting the first and second nonvolatile memories; a plurality of data terminals exposed to outside of the package, the data terminals being connected to the first and second nonvolatile memories through the system bus; and an enable terminal exposed to the outside of the package, the enable terminal being connected to the first and second nonvolatile memories.Type: ApplicationFiled: December 19, 2008Publication date: April 30, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Norihiro FUJITA, Hiroyuki NAGASHIMA, Hiroshi NAKAMURA
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Publication number: 20090103368Abstract: A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.Type: ApplicationFiled: December 19, 2008Publication date: April 23, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mikio OGAWA, Norihiro Fujita, Hiroshi Nakamura
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Publication number: 20090080261Abstract: A nonvolatile semiconductor memory, has a first wire; a second wire adjacent to the first wire; a third wire disposed next to the second wire such that the second wire is disposed between the first wire and the third wire; a power supply circuit for setting each of the wires at a predetermined potential; and a determining circuit for determining presence or absence of a short circuit between the wires.Type: ApplicationFiled: September 23, 2008Publication date: March 26, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Norihiro Fujita, Toshihiko Himeno, Hitoshi Shiga
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Patent number: 7486562Abstract: A semiconductor memory device comprises a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.Type: GrantFiled: August 2, 2005Date of Patent: February 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Mikio Ogawa, Norihiro Fujita, Hiroshi Nakamura
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Patent number: 7486569Abstract: A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.Type: GrantFiled: December 12, 2006Date of Patent: February 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Norihiro Fujita, Hiroyuki Nagashima, Hiroshi Nakamura
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Publication number: 20080170435Abstract: A memory cell array has a plurality of multi-value memory cells arranged therein that can store information of two bits or more in one memory cell as a different page. In each of the data registers, an acceptable number setting register, which temporarily retains data read from the memory cell array, stores multiple acceptable numbers of data states corresponding to each state of threshold voltages of each of the pages in the multi-value memory cells. A selector selects, from the multiple acceptable numbers of data states, an acceptable number of data states for data retained in each of the data registers corresponding to each page of the multi-value memory cells. A comparator compares the number of data states retained in each of the data registers with the acceptable number of data states selected by the selector.Type: ApplicationFiled: January 17, 2008Publication date: July 17, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoya Tokiwa, Norihiro Fujita
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Publication number: 20070163685Abstract: The present invention provides a method of hot pressing using hot rolled and cold rolled steel sheet or Al-based plated steel sheet or Zn-based plated steel sheet enabling a strength of at least 1200 MPa to be obtained after high temperature forming and with extremely little possibility of hydrogen embrittlement and such hot pressed parts, that is, a method of hot pressing a high strength automobile parts comprising using steel sheet containing as steel compositions by wt % C:0.05 to 0.5% or steel sheet plated mainly with Al or Zn to produce automobile members by hot pressing during which making the heating temperature before pressing Ac3 or more to 1100° C. or less, making the hydrogen concentration in the heating atmosphere 6 vol % or less, and making the dew point 10° C. or less and such hot pressed parts.Type: ApplicationFiled: July 15, 2005Publication date: July 19, 2007Inventors: Kazuhisa Kusumi, Jun Maki, Masayuki Abe, Masahiro Ohgami, Norihiro Fujita, Shinya Nakajima
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Publication number: 20070133281Abstract: A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.Type: ApplicationFiled: December 12, 2006Publication date: June 14, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Norihiro FUJITA, Hiroyuki Nagashima, Hiroshi Nakamura
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Publication number: 20060133155Abstract: A nonvolatile semiconductor memory device comprises memory cell array constituted of a plurality of memory blocks which electrically rewritable memory cells are arranged, before erasing data of all of said memory cells in the selected memory block in a plurality of said memory blocks, preprogram is performed to shift all threshold voltages of all of said memory cells in said selected memory blocks to positive.Type: ApplicationFiled: December 5, 2005Publication date: June 22, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Norihiro Fujita, Hiroshi Nakamura
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Publication number: 20060034140Abstract: A semiconductor memory device comprises a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.Type: ApplicationFiled: August 2, 2005Publication date: February 16, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mikio Ogawa, Norihiro Fujita, Hiroshi Nakamura
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Patent number: 6301143Abstract: In an enabling high-speed operation memory cell chip, its cell array is divided, for example, into 4 cell blocks, the first two being arranged side by side, while the second two being arranged side by side under the first two. The row decoder groups are each arranged between the cell blocks provided in row direction. The column decoder groups and the sense amplifier groups are respectively arranged between the cell blocks provided in column direction. Further, the peripheral circuit area is provided between the cell blocks provided in column direction so that the predecoder groups, address input circuit groups and data input/output circuit groups are arranged in line therein.Type: GrantFiled: August 25, 2000Date of Patent: October 9, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Norihiro Fujita, Masami Masuda