Abstract: According to one embodiment, a command processing device includes a frontend part and a backend part. The frontend part is configured to execute a data communication with respect to a host based on a predetermined communication protocol, and accept a request of an execution of first and second commands from the backend part. The backend part is configured to queue commands including the first and second commands, and execute a data communication according to the first command with respect to an attachment device and a data communication according to the second command with respect to the attachment device in parallel.

Abstract: According to one embodiment, a controller switches modes including a normal operating mode in which power resources of a volatile memory, a data storage unit, and a power control unit are all ON, a first mode in which the power resource of the volatile memory is OFF, and the power resources of the data storage unit and the power control unit are both ON, and a second mode in which the power resources of the volatile memory and the data storage unit are both OFF, and the power resource of the power control unit is ON. Upon receiving a low power consumption instruction command from a host, the controller stores management information to return to the normal operating mode into the volatile storage unit, and shifts the state of the memory system from the normal operating mode to the first mode.

Abstract: According to one embodiment, an information processing system includes a first storage device, a second storage device, and a host device that controls the first and second storage devices. When a first condition is satisfied, the host device transfers data stored in the first storage device to the second storage device, and thereafter, turns off the first storage device. When it is required to perform data processing by the first storage device, the host device turns on the first storage device.

Abstract: According to one embodiment, a command processing device includes a frontend part and a backend part. The frontend part is configured to execute a data communication with respect to a host based on a predetermined communication protocol, and accept a request of an execution of first and second commands from the backend part. The backend part is configured to queue commands including the first and second commands, and execute a data communication according to the first command with respect to an attachment device and a data communication according to the second command with respect to the attachment device in parallel.

Abstract: According to one embodiment, a data transfer control device complying with a communication protocol which executes an update of information from an attachment device in a predetermined area of a system memory, the device includes a receiving part receiving the information from the attachment device, a transferring part transferring the information in the predetermined area, the information from the transferring part overwritten in the predetermined area sequentially, and a determining part inhibiting a transfer of the information in the transferring part to omit the update of the information in the predetermined area.

Abstract: According to one embodiment, there is provided a memory system including a first storage medium group, a second storage medium group, and a controller. The controller is configured to multiply write the same data to the first storage medium group and the second storage medium group. And the controller is configured to transmit data read out from a storage medium group selected from the first storage medium group and the second storage medium group to a host according to a progress status of a readout process for the first storage medium group and the second storage medium group when receiving a readout command of stored data in the first storage medium group and the second storage medium group from the host.

Abstract: According to one embodiment, a memory system has a data transfer device which includes a first command generating unit, a second command generating unit, a first storage unit, a second storage unit, and a nonvolatile memory managing unit. The first command generator generates a first command for reading out data from a nonvolatile memory to a host apparatus. The second command generator generates a second command for internal processing of the memory system associated with a temporary memory and the nonvolatile memory. The first memory has a queue structure configured to store the first command. The second memory has a queue structure configured to store the second command. The memory manager is configured to read out the first command stored in the first memory in priority to the second command stored in the second memory and to transmit read-out command to the nonvolatile memory.

Abstract: According to one embodiment, a storage device has a plurality of memory modules and a memory controller. The memory controller has a first unit configured to receive data to be stored in the memory modules from a host device as a write data stream and transmit data read from the memory modules to the host device as a read data stream, a second unit having a plurality of subunits, each of which is configured to write data in one of the memory modules corresponding to the subunit and read data from one of the memory modules corresponding to the subunit, and a data stream converter configured to parallelize the write data stream into a plurality of data blocks each of which is to be stored in one of the memory modules and to serialize a plurality of data blocks read from the memory modules into the read data stream.

Abstract: According to one embodiment, a memory system comprises a nonvolatile memory, a first volatile memory which stores management information to manage the nonvolatile memory, a controller which controls operations of the nonvolatile memory and the first volatile memory, and a power supply circuit which makes power supplied to part of the first volatile memory zero in accordance with a data capacity of the management information in response to a request from the controller.

Abstract: Created is transfer order information indicating an order of transfer from multiple memory areas in accordance with an order of logical addresses and memory locations which are specified by read commands. Readout from the multiple memory areas in accordance with the transfer order information is performed by controlling memory controllers in accordance with the created transfer order information.

Abstract: According to one embodiment, a memory system includes a chip including a cell array and first and second caches configured to hold data read out from the cell array; an interface configured to manage a first and a second addresses; a controller configured to issue a readout request to the interface; and a buffer configured to hold the data from the chip. The interface transfers the data in the first cache to the buffer without reading out the data from the cell array if the readout address matches the first address, transfers the data in the second cache to the buffer without reading out the data from the cell array if the readout address matches the second address, and reads out the data from the cell array and transfers the data to the buffer if the readout address does not match either one of the first or second address.

Abstract: According to one embodiment, a memory system includes a chip including a cell array and first and second caches configured to hold data read out from the cell array; an interface configured to manage a first and a second addresses; a controller configured to issue a readout request to the interface; and a buffer configured to hold the data from the chip. The interface transfers the data in the first cache to the buffer without reading out the data from the cell array if the readout address matches the first address, transfers the data in the second cache to the buffer without reading out the data from the cell array if the readout address matches the second address, and reads out the data from the cell array and transfers the data to the buffer if the readout address does not match either one of the first or second address.

Abstract: According to one embodiment, a controller reads out the non-volatile address management information required to execute one of the read commands into an address information cache and retrieves data from the nonvolatile memory according to the volatile address management information stored in the address information cache. In addition, the controller among the read commands stored in the command queue, preferentially executes the read command whose logical addresses are all found in the volatile address management information.

Abstract: According to one embodiment, a memory system has a data transfer device which includes a first command generating unit, a second command generating unit, a first storage unit, a second storage unit, and a nonvolatile memory managing unit. The first command generator generates a first command for reading out data from a nonvolatile memory to a host apparatus. The second command generator generates a second command for internal processing of the memory system associated with a temporary memory and the nonvolatile memory. The first memory has a queue structure configured to store the first command. The second memory has a queue structure configured to store the second command. The memory manager is configured to read out the first command stored in the first memory in priority to the second command stored in the second memory and to transmit read-out command to the nonvolatile memory.

Abstract: According to one embodiment, a memory system includes a chip including a cell array and first and second caches configured to hold data read out from the cell array; an interface configured to manage a first and a second addresses; a controller configured to issue a readout request to the interface; and a buffer configured to hold the data from the chip. The interface transfers the data in the first cache to the buffer without reading out the data from the cell array if the readout address matches the first address, transfers the data in the second cache to the buffer without reading out the data from the cell array if the readout address matches the second address, and reads out the data from the cell array and transfers the data to the buffer if the readout address does not match either one of the first or second address.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a resource managing unit that reclaims resources associated with the non-volatile memory and increases the resources, when the usage of the resources associated with the non-volatile memory reaches the predetermined amount, a transmission rate setting unit that calculates a setting value of the transmission rate to receive the write data from a host device, and a transmission control unit that receives the write data from the host device and transmits the received write data to the non-volatile memory. The transmission rate setting unit calculates a small setting value when the usage of the resources associated with the non-volatile memory increases. The transmission control unit executes the reception of the write data from the host device at the transmission rate of the setting value, while the resource managing unit reclaims the resources.

Abstract: Created is transfer order information indicating an order of transfer from multiple memory areas in accordance with an order of logical addresses and memory locations which are specified by read commands. Readout from the multiple memory areas in accordance with the transfer order information is performed by controlling memory controllers in accordance with the created transfer order information.

Abstract: A memory controller includes a buffer to which data, which is to be transferred to a memory, is input, an ECC parity generating unit which generates an ECC parity in units of a predetermined data length from the data which is to be transferred to the memory, and a memory interface which adds the generated ECC parity in units of the predetermined data length, and delivers the data with the ECC parity to the memory. When a data length of the data which is to be transferred to the memory is less than the predetermined data length, the ECC parity generating unit regards data of a part that is short of the predetermined data length as “0”, and generates the ECC parity from the data of less than the predetermined data length.

Abstract: A third insulator of a washer switch constituting the second electrical switching unit is set to be long in the axial direction, the insulator is provided with fixed contacts extending in the axial direction and at the same time a base portion thereof is provided with connecting terminals, and the connecting terminals are disposed in the vicinity of the connecting terminals of a wiper switch constituting the first electrical switching unit. Second lead wire and third lead wire are connected to the connecting terminals, respectively.

Abstract: A slider operated to slide by a lever for light is constructed by an arrangement capable of being integrated by inserting a portion thereof to a cylindrical portion of a slide guide portion provided at an insulator. Thereby, an integrating performance can be promoted in comparison with that of a structure of squeezing the slider by 2 parts. Further, a clearance in a height direction of the slider can be controlled by one part of the insulator, and therefore, a variation thereof can be reduced in comparison with that of the case of controlling the clearance by 2 parts.