Patents by Inventor Norio Fukasawa

Norio Fukasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6471501
    Abstract: A mold for press-molding a resin package body includes a lower mold and an upper mold, wherein the upper mold includes a press plate held in a tiltable manner with respect to a press head used for urging the upper mold against the lower mold and a lock mechanism for locking the press plate. The lower mold includes an inner die carrying a semiconductor device and a resin tablet and an outer die surrounding the inner die in a manner movable up and down with respect to the inner die. In operation, the press plate is first engaged with the outer die in the unlocked state to achieve an exact parallelism with respect to the inner die, and after locking the press plate and melting the resin tablet, the press plate is urged further toward the inner die while simultaneously lowering the outer die such that the space formed by the lower die, outer die and the press plate for accommodating a semiconductor chip is collapsed.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: October 29, 2002
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Shinma, Muneharu Morioka, Norio Fukasawa, Yuzo Hamanaka, Tadashi Uno, Hirohisa Matsuki, Kenichi Nagashige
  • Patent number: 6469370
    Abstract: In a semiconductor device of the present invention and a production method thereof, an electronic circuit is provided in a semiconductor substrate, the electronic circuit having terminals. An internal wiring pattern is provided in the substrate, the internal wiring pattern being connected to the electronic circuit terminals. A protective layer is provided on the substrate, the protective layer covering the substrate. Vias are provided on the substrate so as to project from the protective layer, the vias being connected to the internal wiring pattern at arbitrary positions on the substrate. An external wiring pattern is provided on the protective layer, the external wiring pattern being connected to the vias. Projection electrodes are connected to the external wiring pattern, the projection electrodes having a predetermined height above the external wiring pattern.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: October 22, 2002
    Assignee: Fujitsu Limited
    Inventors: Toshimi Kawahara, Hirohisa Matsuki, Yasuhiro Shinma, Yoshiyuki Yoneda, Norio Fukasawa, Yuzo Hamanaka, Kenichi Nagashige, Takashi Hozumi
  • Patent number: 6455920
    Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: September 24, 2002
    Assignee: Fujitsu Limited
    Inventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
  • Publication number: 20020127776
    Abstract: A semiconductor device includes a semiconductor element having a circuit surface on which a projection electrode is formed, a seal resin which seals the circuit surface of the semiconductor element while exposing at least an end part of the projection electrode, a connect surface that is to face a board when the semiconductor device is implemented on the board, a back surface which is opposite to the connect surface, a side surface arranged between the connect surface and the back surface, and an organic material layer formed on the side surface.
    Type: Application
    Filed: October 4, 2001
    Publication date: September 12, 2002
    Applicant: Fujitsu Limited
    Inventors: Shinsuke Nakajo, Norio Fukasawa, Takashi Hozumi, Shinya Nakaseko
  • Patent number: 6437432
    Abstract: A semiconductor device is provided, which device includes a semiconductor substrate including a plurality of signal pads and ground pads, an insulating film formed on the semiconductor substrate, a conductive metal film formed on the insulating film and electrically connected to the ground pads and a plurality of first interconnection lines electrically connected to the signal pads and insulated from the conductive metal film. The conductive metal film is formed over a region including the first interconnection lines in a plan view of the semiconductor device.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: August 20, 2002
    Assignee: Fujitsu Limited
    Inventors: Masamitsu Ikumo, Toshimi Kawahara, Norio Fukasawa, Kenichi Nagashige
  • Publication number: 20020089040
    Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.
    Type: Application
    Filed: March 15, 2002
    Publication date: July 11, 2002
    Applicant: FIJITSU LIMITED
    Inventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
  • Publication number: 20020089054
    Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.
    Type: Application
    Filed: March 15, 2002
    Publication date: July 11, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Norio Fukasawa, Hirohisa Matsuki, Kenichi Nagashige, Yuzo Hamanaka, Muneharu Morioka
  • Patent number: 6388461
    Abstract: A semiconductor inspection apparatus performs a test on a to-be-inspected device which has a spherical connection terminal. This apparatus includes a conductor layer formed on a supporting film. The conductor layer has a connection portion. The spherical connection terminal is connected to the connection portion. At least a shape of the connection portion is changeable. The apparatus further includes a shock absorbing member, made of an elastically deformable and insulating material, for at least supporting the connection portion.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: May 14, 2002
    Assignee: Fujitsu Limited
    Inventors: Norio Fukasawa, Yukinori Sumi
  • Publication number: 20020036509
    Abstract: A semiconductor test apparatus tests a semiconductor device having plate connection terminals. The apparatus includes a test substrate having deformable connection parts connected with the plate connection terminals, and an upholding substrate which has upholding parts formed to project at a position that faces the connection part and which urges, in cooperation with the test substrate, the connection parts toward the plate connection terminals of the semiconductor device so as to electrically connect the connection parts to the plate connection terminals.
    Type: Application
    Filed: October 31, 2001
    Publication date: March 28, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Norio Fukasawa, Yukinori Sumi
  • Publication number: 20020030258
    Abstract: A method includes a resin sealing step of placing, in a cavity 28 of a mold 20, a substrate 16 to which semiconductor elements 11 on which bumps 12 are arranged, a resin sealing step of supplying resin 35 to positions of the bumps 12 so that a resin layer 13 sealing the bumps 12 is formed, a protruding electrode exposing step of exposing at least ends of the bumps 12 sealed by the resin layer 13 so that ends of the bumps 12 are exposed from the resin layer 13, and a separating step of cutting the substrate 16 together with the resin layer 13 so that the semiconductor elements 11 are separated from each other.
    Type: Application
    Filed: January 23, 2001
    Publication date: March 14, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Norio Fukasawa, Toshimi Kawahara, Muneharu Morioka, Mitsunada Osawa, Yasuhiro Shinma, Hirohisa Matsuki, Masanori Onodera, Junichi Kasai, Shigeyuki Maruyama, Masao Sakuma, Yoshimi Suzuki, Masashi Takenaka
  • Patent number: 6333638
    Abstract: A semiconductor test apparatus tests a semiconductor device having plate connection terminals. The apparatus includes a test substrate having deformable connection parts connected with the plate connection terminals, and an upholding substrate which has upholding parts formed to project at a position that faces the connection part and which urges, in cooperation with the test substrate, the connection parts toward the plate connection terminals of the semiconductor device so as to electrically connect the connection parts to the plate connection terminals.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: December 25, 2001
    Assignee: Fujitsu Limited
    Inventors: Norio Fukasawa, Yukinori Sumi
  • Publication number: 20010023981
    Abstract: A semiconductor device is provided, which device includes a semiconductor substrate including a plurality of signal pads and ground pads, an insulating film formed on the semiconductor substrate, a conductive metal film formed on the insulating film and electrically connected to the ground pads and a plurality of first interconnection lines electrically connected to the signal pads and insulated from the conductive metal film. The conductive metal film is formed over a region including the first interconnection lines in a plan view of the semiconductor device.
    Type: Application
    Filed: December 26, 2000
    Publication date: September 27, 2001
    Inventors: Masamitsu Ikumo, Toshimi Kawahara, Norio Fukasawa, Kenichi Nagashige
  • Publication number: 20010011772
    Abstract: A semiconductor device has a resin package layer on a principal surface of a semiconductor chip, on which a number of bump electrodes are formed, wherein the semiconductor device has a chamfer surface or a stepped surface on a top edge part such that the external shock or stress applied to such an edge part is dissipated by the chamfer surface of the stepped surface.
    Type: Application
    Filed: September 25, 1998
    Publication date: August 9, 2001
    Applicant: FUJITSU LIMITED
    Inventors: NORIO FUKASAWA, HIROHISA MATSUKI, KENICHI NAGASHIGE, YUZO HAMANAKA, MUNEHARU MORIOKA
  • Publication number: 20010010469
    Abstract: A semiconductor inspection apparatus performs a test on a to-be-inspected device which has a spherical connection terminal. This apparatus includes a conductor layer formed on a supporting film. The conductor layer has a connection portion. The spherical connection terminal is connected to said connection portion. At least a shape of said connection portion is changeable. The apparatus further includes a shock absorbing member, made of an elastically deformable and insulating material, for at least supporting said connection portion.
    Type: Application
    Filed: March 14, 2001
    Publication date: August 2, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Norio Fukasawa, Yukinori Sumi
  • Patent number: 6246249
    Abstract: A semiconductor inspection apparatus performs a test on a to-be-inspected device which has a spherical connection terminal. This apparatus includes a conductor layer formed on a supporting film. The conductor layer has a connection portion. The spherical connection terminal is connected to the connection portion. At least a shape of the connection portion is changeable. The apparatus further includes a shock absorbing member, made of an elastically deformable and insulating material, for at least supporting the connection portion.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: June 12, 2001
    Assignee: Fujitsu Limited
    Inventors: Norio Fukasawa, Yukinori Sumi
  • Publication number: 20010003049
    Abstract: A method includes a resin sealing step of placing, in a cavity 28 of a mold 20, a substrate 16 to which semiconductor elements 11 on which bumps 12 are arranged, a resin sealing step of supplying resin 35 to positions of the bumps 12 so that a resin layer 13 sealing the bumps 12 is formed, a protruding electrode exposing step of exposing at least ends of the bumps 12 sealed by the resin layer 13 so that ends of the bumps 12 are exposed from the resin layer 13, and a separating step of cutting the substrate 16 together with the resin layer 13 so that the semiconductor elements 11 are separated from each other.
    Type: Application
    Filed: May 15, 1998
    Publication date: June 7, 2001
    Inventors: NORIO FUKASAWA, TOSHIMI KAWAHARA, MUNEHARU MORIOKA, MITSUNADA OSAWA, YASUHIRO SHINMA, HIROHISA MATSUKI, MASANORI ONODERA, JUNICHI KASAI, SHIGEYUKI MARUYAMA, MASAO SAKUMA, YOSHIMI SUZUKI, MASASHI TAKENAKA
  • Patent number: 6188528
    Abstract: An optical lens composed of a transparent material, wherein one surface thereof on a light source side is a convex aspherical surface of rotation symmetry defined by a function relative to the radial distance from an optical axis. The aspherical surface is shaped to be a curved one without any stepped region with regard to the radial direction in the defined area, and has a portion where the derivatives of the function are discontinuous at a predetermined radial position. Although not equipped with an iris diaphragm, this optical lens is capable of eliminating an incident light beam outside the optical effective surface thereof without deteriorating the optical characteristics.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: February 13, 2001
    Assignee: Sony Corporation
    Inventors: Takatoshi Yamada, Norio Fukasawa
  • Patent number: 6013944
    Abstract: A semiconductor device including a semiconductor chip; a plurality of electrodes provided on a surface of the semiconductor chip; an insulative board which includes a plurality of conductive patterns, one end of each of the plurality of conductive patterns being protruded from a periphery of the insulative board so as to function as an outer terminal; a connecting element for electrically connecting the outer terminal to a corresponding one of the plurality of electrodes; and a conductive element which is in electrical contact with a corresponding one of the plurality of conductive patterns.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: January 11, 2000
    Assignee: Fujitsu Limited
    Inventors: Susumu Moriya, Norio Fukasawa, Shirou Youda
  • Patent number: 5767528
    Abstract: A semiconductor device includes a semiconductor element; a wiring board including a base film on which a plurality of leads are provided; projecting electrodes, provided in an array, projecting from a lower surface of the wiring board; a plurality of leads, each of which has an inner lead portion connected to the semiconductor element and an outer lead portion connected to the projecting electrodes; a mounting hole provided in the base film for mounting the semiconductor element; and a supporting member supporting the wiring board and having a cavity for accommodating the semiconductor element in a position corresponding to the mounting hole. A pad portion for measurement is provided at a position spaced from the outer lead portion.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: June 16, 1998
    Assignee: Fujitsu Limited
    Inventors: Yukinori Sumi, Norio Fukasawa