Patents by Inventor Norio Hayafuji

Norio Hayafuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5394417
    Abstract: A semiconductor laser for producing visible light includes a first conductivity type semiconductor substrate; a first conductivity type semiconductor first cladding layer, a semiconductor active layer of GaAs.sub.1-y P.sub.y (y.ltoreq.0.45), and a second conductivity type second cladding layer, the first cladding layer, the active layer, and the second cladding layer being successively disposed on the semiconductor substrate, the first and second cladding layers having substantially the same composition and a different composition from the active layer, thereby forming heterojunctions with the active layer, and having a lattice constant different from the lattice constant of the active layer and introducing stress into the active layer without producing dislocations in the active layer; and first and second electrodes electrically connected to the substrate and the second cladding layer, respectively.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: February 28, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masayoshi Takemi, Norio Hayafuji, Wataru Susaki
  • Patent number: 5387544
    Abstract: While producing a III-V compound semiconductor layer, carbon is added to group III and V elements to control the p type conductivity of the semiconductor layer, forming a p type region. Then, a small amount of n type dopant is added to the group III and V elements together with the carbon to control the n type conductivity of the semiconductor layer, forming an n type region. Therefore, a sharp and precisely-controlled doping profile is obtained in the vicinity of the p-n junction, resulting in a semiconductor device having high initial-performance and high reliability.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: February 7, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Norio Hayafuji
  • Patent number: 5357535
    Abstract: In accordance with the invention, after a crystal growth is carried out successively to produce at least a first conductivity type lower cladding layer, and active layer, a second conductivity type first upper cladding layer of AlGaAs having an AlAs composition ratio of 0.38 to 0.6, an etching stopper layer of AlGaAs having an AlAs composition ratio of more than 0.6, and a second conductivity type second upper cladding layer of AlGaAs having an AlAs composition ratio of 0.38 to 0.6, the second upper cladding layer is selectively etched using an etchant including an organic acid and hydrogen peroxide, thereby forming a ridge. As a result, a ridge-type semiconductor laser device which has a desirable laser structure and an oscillation wavelength below 830 nm can be produced easily with improved controllability and reproducibility.
    Type: Grant
    Filed: January 6, 1993
    Date of Patent: October 18, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akihiro Shima, Takeshi Miura, Tomoko Kadowaki, Norio Hayafuji
  • Patent number: 5316967
    Abstract: In a method for producing a semiconductor device, a first semiconductor layer is epitaxially grown on a semiconductor substrate, an insulating film pattern is formed on the first semiconductor layer, and portions of the first semiconductor layer are removed by wet etching using the insulating film pattern as a mask to leave a ridge having a reverse mesa shape and a width. Ends of the insulating film pattern are removed by etching to approximately the width of the ridge, a second semiconductor layer is epitaxially grown on opposite sides of the ridge, and a third semiconductor layer is epitaxially grown on the ridge and the second semiconductor layer. The second semiconductor layer is evenly grown without concave portions at opposite sides of the ridge. In addition, the third semiconductor layer is evenly grown on the ridge and the second semiconductor layer, and an electrode reliably connects the surface of the third semiconductor layer.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: May 31, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuaki Kaneno, Hirotaka Kizuki, Norio Hayafuji, Tetsuo Shiba, Hitoshi Tada
  • Patent number: 5315133
    Abstract: While depositing a III-V compound semiconductor layer from a vapor, carbon is added to group III and V elements to produce a p type conductivity region in the depositing semiconductor layer. Then, a small amount of n type dopant is added to the group III and V elements together with the carbon to produce an n type conductivity region in the depositing semiconductor layer. A sharp and precisely controlled doping profile is produced in the vicinity of a p-n junction, resulting in a semiconductor device having good initial performance and high reliability.
    Type: Grant
    Filed: August 13, 1992
    Date of Patent: May 24, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Norio Hayafuji
  • Patent number: 5279077
    Abstract: In a method for forming a semiconductor wafer with an orientation flat along a cleavage plane, a groove or hole is formed in the substrate on a line along which the substrate is cleaved to form an orientation flat and the substrate is treated to produce a mirrorlike surface. Then, the substrate having the mirrorlike surface is cleaved from the groove or hole to form the orientation flat. Accordingly, edges of the cleavage plane are not rounded due to the surface treatment. In addition, the substrate is easily cleaved along the cleavage plane from the groove or the hole. As a result, a semiconductor wafer having a sharp cleavage plane as an orientation flat is produced with improved yield, and alignment is performed with high precision in a subsequent process, such as photolithography.
    Type: Grant
    Filed: November 16, 1992
    Date of Patent: January 18, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Motoharu Miyashita, Norio Hayafuji, Yutaka Mihashi
  • Patent number: 5100480
    Abstract: A solar cell includes an insulating or semi-insulating substrate having a pair of through holes, an n type semiconductor layer disposed on the front surface of the substrate, and a p type semiconductor layer disposed on the substrate in the first hole and on the n type semiconductor layer. An n side electrode is formed on the surface of the n type semiconductor layer in the second hole and also on a part of the back surface of the substrate. A p side electrode is formed on the surface of the p type semiconductor layer in the first hole and also on the back surface of the substrate. In connecting a plurality of solar cells in a wafer in series, a trench reaching the substrate is formed between adjacent solar cells.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: March 31, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Norio Hayafuji