Patents by Inventor Norio Nakamura

Norio Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6155080
    Abstract: Inserting knitting needles into a knitting machine in regular order, without requiring experience of the worker, is enabled by the use of a knitting needle arranging apparatus which is comprising:(a) a series of knitting needle supplying means for sequentially pushing one or plural knitting needles in one direction;(b) knitting needle stacking means for sequentially stacking and holding the pushed knitting needles in the thickness direction of the knitting needle in cooperation with each of the series of the knitting needle supplying means; and(c) means for moving the knitting needle stacking means from a cooperation state with one of the knitting needle supplying means so as to cooperate with predetermined knitting needle supplying means.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: December 5, 2000
    Assignee: Teijin Limited
    Inventors: Takeshi Yamaguchi, Norio Nakamura
  • Patent number: 6141163
    Abstract: A phase-locked loop circuit and recording/reproducing apparatus of this invention include a distributor (11) for receiving reproduction data to distribute and output it as n reproduction data, a phase comparator group (6) having n phase comparators for sequentially receiving the distributed reproduction data to compare the phases of the reproduction data with that of a reproduction clock, a frequency comparator (5) for receiving a reference clock and the reproduction clock to compare their frequencies, a selector (7) for receiving a switching control signal, the phase comparison result, and the frequency comparison result, and selecting either one of the phase comparison result and the frequency comparison result to output the selected one as a voltage signal, a charge pump (8) for receiving the voltage signal and converting it into a current signal to output the current signal, a loop filter (9) for receiving the current signal to output a low-frequency voltage signal, and a VCO (10) for receiving the low-fr
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: October 31, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norio Nakamura, Toshio Shiramatsu
  • Patent number: 6128166
    Abstract: According to this invention, there is provided a magnetic recording/reproducing system having a recording head for recording a signal in a magnetic recording medium along recording tracks having a predetermined track pitch and a reproducing head for reproducing the recorded signal. A relationship between a recording track width Tw of the recording head and a reproduction width Tr of the reproducing head is defined as Tr>Tw. When conditions g<(1500/Hc-Hc/4000.pi.+0.3)/(Hc/400.pi.-1/2) and g.gtoreq.(1500/Hc-Hc/4000.pi.+0.3-Tp+Tw)/(Hc/400.pi.-1/2) are satisfied, an erase region is formed between the recording tracks. In this case, the gap length of the recording head is represented by g [.mu.m], the recording track width is represented by Tw [.mu.m], the track pitch is represented by Tp [.mu.m], and the coercive force of the recording medium is represented by Hc [Oe].
    Type: Grant
    Filed: May 18, 1995
    Date of Patent: October 3, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoichiro Tanaka, Norio Nakamura, Kazunori Moriya, Yuji Kubota, Takashi Hikosaka
  • Patent number: 6096312
    Abstract: An agent for preventing or treating AIDS which contains as its effective component an anti-Fas ligand antibody, and the method for preventing and treating AIDS by using such drug.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: August 1, 2000
    Assignees: Mochida Pharmaceutical Co., Ltd., Osaka Bioscience Institute
    Inventors: Norio Nakamura, Kamon Shirakawa, Tomokazu Matsusue, Shigekazu Nagata, Man Sung Co, Maximiliano Vasquez
  • Patent number: 6084470
    Abstract: In this filter circuit, the emitter of a transistor Q1 is connected to the collector of a transistor Q2, and the base of the transistor Q2 is connected to the emitter of a transistor Q3 and the collector of a transistor Q4. The base of the transistor Q4 is connected to the collector of the transistor Q2. A capacitor C1 is connected between the emitters of the transistors Q2 and Q4, and a capacitor C2 is connected between the collectors of the transistors Q2 and Q4. With this arrangement, the filter circuit consumes a small power, is hardly influenced by the parasitic capacitance, can operate at high frequencies, and has a wide dynamic range.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: July 4, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshio Shiramatsu, Norio Nakamura, Nobuyasu Goto
  • Patent number: 6077747
    Abstract: In a semiconductor device manufacturing method, a gate insulating film (2), a first gate electrode forming material film (4), a first film (10) and a second film (11) are formed on a semiconductor substrate (1), then a channel region (3) is formed by doping the substrate (1) with impurities through an opening portion formed in the second film (11) which is formed at inner edge of an opening of the first film (10), then a second gate electrode forming material film (9) formed thereon is left within the opening portion of the second film (11) through etching back thereof, then a groove is formed by removing the second film (11) with the remaining film (9) and the first film (10) used as an etching mask, then a low-concentration impurity diffusion layer (12) and an impurity layer (13) of the opposite conduction type to that of the layer (12) are formed in the substrate (1), then a portion of the film (4) exposed at the bottom of the groove is removed, then a side wall (14) of insulating material is formed in the
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: June 20, 2000
    Assignee: NEC Corporation
    Inventor: Norio Nakamura
  • Patent number: 6060887
    Abstract: A circuit and method for detecting an abnormality in a recording head, wherein a voltage detection circuit detects a counter electromotive voltage generated across the two terminals of a recording head to which a recording current is supplied from a recording circuit; a processing circuit generates the maximum, minimum, and mean voltages from the counter electromotive voltage; a discrimination circuit using these voltages determines whether an abnormality occurs in the recording head. An output circuit outputs the result. With this operation, an abnormality in the recording head having two terminals in an MR head can be detected with a high precision.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: May 9, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norio Nakamura, Nobuyasu Goto
  • Patent number: 5923084
    Abstract: A semiconductor device comprising a low-heat-resistance heat discharging route suitable for small semiconductor devices, such as an IC card, is disclosed. Heat arising from electronic parts is efficiently dispersed to the outside, thereby accomplishing a decrease in size and a heightening of function. In a specific embodiment, a CPU is mounted on a substrate in a position of thermal via holes. A high-heat-conducting material such as semifluid silicone rubber is placed between a CPU mounting face of the substrate and lower panel located on the opposite side of the substrate. The high-heat-conducting material is a filler having the ability to change shape and the property of electrical nonconductivity. A greater part of the heat arising from the CPU is transmitted through the thermal via holes from the CPU mounting face of the substrate to the opposite side, and further to the high-heat-conducting material which conveys the heat to the lower panel.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: July 13, 1999
    Assignee: Seiko Epson Corporation
    Inventors: Kazuaki Inoue, Hiroyuki Yamashita, Norio Nakamura, Hiroyuki Yoda
  • Patent number: 5866634
    Abstract: The present invention provides a novel biodegradable polymer compositions effecting superiority in elongation at break, Izod impact strength and mold releasability which has not been obtained before the past and provides a biodegradable shrink film exceling in transparency, strength, flexibility, mold releasability and shrinkability by applying the biodegradable polymer composition to the shrink film. Thus, the biodegradable polymer compositions are provided which comprise as a main component a mixture of two or more of polylactic acids, glycol/aliphatic dicarboxylic acid copolymers and polycaprolactones and these biodegradable polymer compositions are applied to shrink films.
    Type: Grant
    Filed: August 28, 1996
    Date of Patent: February 2, 1999
    Assignee: Shin-Etsu Chemical Co., Ltd
    Inventors: Yuji Tokushige, Makoto Ooura, Norio Nakamura, Shuhei Ueda
  • Patent number: 5864463
    Abstract: A thin and small computer system that can be used generally for control of equipment or the like, includes a CPU chip, peripheral control chips, and other components mounted in the form of a bare chip, whereby a computer system having a so-called hierarchy architecture can be incorporated in an IC card-like casing. Computer system components are affixedly attached to a double-sided printed wiring board. Electronic components may be attached to the printed wiring board in a bare form and then at least partially sealed with a resin. A system may further include a second printed board which is independent from the first printed board and adhesively attached to a inner surface of the casing and connected to the first printed board by a flexible member. In addition the second circuit board may include structure which enables it to connect to an apparatus for programming an electronic component attached thereto.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: January 26, 1999
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Tsukada, Norio Nakamura, Minoru Nimura, Hiroyuki Suemori, Tomio Kamihata, Mutsuaki Yamazaki
  • Patent number: 5861433
    Abstract: A composition such as foods, drinks, pharmaceutical composition, for prevention or improvement of inflammation such as chronic inflammation, comprising an omega 9 series unsaturated fatty acid such as 6,9-octadecadienoic acid, 8,11-eicosadienoic acid, 5,8,11-eicosatrienoic acid etc.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: January 19, 1999
    Assignee: Suntory Limited
    Inventors: Kengo Akimoto, Hiroshi Kawashima, Satomichi Yoshimura, Masashi Matsui, Tomohito Hamazaki, Shigeki Sawazaki, Norio Nakamura
  • Patent number: 5834512
    Abstract: A composition such as foods, drinks, pharmaceutical composition, for prevention or improvement of allergy, comprising an omega 9 series unsaturated fatty acid such as 6,9-octadecadienoic acid, 8,11-eicosadienoic acid, 5,8,11-eicosatrienoic acid etc.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: November 10, 1998
    Assignee: Suntory Limited
    Inventors: Kengo Akimoto, Hiroshi Kawashima, Satomichi Yoshimura, Masashi Matsui, Tomohito Hamazaki, Shigeki Sawazaki, Norio Nakamura
  • Patent number: 5821614
    Abstract: A card type semiconductor device includes a main circuit board and a first sub-circuit-board equipped with a main memory. The main circuit board is connected to the first sub-circuit-board through an FPC. A first TCP equipped with the CPU and a second TCP equipped with the I/O sub-system chip are mounted on the top and bottom surfaces of the main circuit board. The first and second TCPs are mounted to directly oppose each other. The card type semiconductor device is used as a card type computer. The main circuit board and the sub-circuit-board face each other by bending the FPC and enclosing the main circuit board and the sub-circuit-board in a card-shaped thin housing. The card type semiconductor device achieves a high density packaging in a small form factor.
    Type: Grant
    Filed: May 5, 1995
    Date of Patent: October 13, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Nobuaki Hashimoto, Norio Nakamura, Hiroyuki Suemori, Hiroshi Sugai, Norio Imaoka, Kazuyoshi Noake
  • Patent number: 5812337
    Abstract: A magnetic disk drive capable of performing a head seek at high speed even when a track pitch of the recording track of the magnetic disk is narrowed. The structure eliminates incomplete erasure caused by a positioning error of a recording head and prevents side-fringe magnetic field from erasing a signal on an adjacent track in order to obtain a larger reproduction output.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: September 22, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoichiro Tanaka, Yuji Kubota, Norio Nakamura
  • Patent number: 5779337
    Abstract: A plane light source unit includes a tubular light source, and a light guide. The light guide has a light emitting surface and a reflecting surface in addition to a light incident face placed near the tubular light source to receive light emitted from the tubular light source. The light guide has a plurality of projections or grooves arrayed on the light emitting surface to extend parallel to each other along a longitudinal direction of the tubular light source so as to cause the light incident from the light incident face to emerge from the light emitting surface. The height or depth of each of the projections or grooves increases from the central portion to the two end portions in the longitudinal direction of the tubular light source.
    Type: Grant
    Filed: July 31, 1996
    Date of Patent: July 14, 1998
    Assignees: Konica Corporation, Toshiba Corporation
    Inventors: Shinichiro Saito, Norio Nakamura, Yasuo Shono, Yoshinori Higuchi, Atsunori Ohyama
  • Patent number: 5726220
    Abstract: The present invention provides polylactic compositions effecting an excellent mold releasability upon processing and significantly improved elongation at break and impact strength without affecting the transparency. Also provided is a shrink film which decomposes under the natural environment and has excellent transparency, flexibility, shrinkability and mold releasability upon processing by applying the polylactic acid composition to a shrink film. There is provided a biodegradable polymer composition comprising 100 parts by weight of polylactic acid and 5 to 70 parts by weight of EVA. Further, a biodegradable polymer composition is provided comprising the polymer composition with one or more additives selected from the group consisting of 0.05 to 5 parts by weight of a lubricant, 1 to 50 parts by weight of plasticizer, 0.5 to 5 parts by weight of thermal stabilizer and 0.05 to 5 parts by weight of mold releasing agent. These biodegradable polymer compositions are applied to shrink films.
    Type: Grant
    Filed: August 28, 1996
    Date of Patent: March 10, 1998
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Yuji Tokushige, Norio Nakamura, Yoichi Tanifuji, Shuhei Ueda
  • Patent number: 5712739
    Abstract: A magnetic disk drive system for writing data into a disk-shaped magnetic medium and reading data stored therein, comprises a first terminal, a second terminal, and at least one third terminal, a composite head unit including an inductive write head and at least one magnetoresistive read head which are connected in series between the first and second terminals, and at least one common connection node connected to the at least one third terminal, and a driving circuit connected to the first through third terminals.
    Type: Grant
    Filed: November 8, 1994
    Date of Patent: January 27, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norio Nakamura, Yusuke Ohinata, Junichi Akiyama, Nobuyasu Goto
  • Patent number: 5710693
    Abstract: A thin and small computer system that can be used generally for control of equipment or the like, includes a CPU chip, peripheral control chips, and other components mounted in the form of a bare chip, whereby a computer system having a so-called hierarchy architecture can be incorporated in an IC card-like casing. Computer system components are affixedly attached to a double-sided printed wiring board. Electronic components may be attached to the printed wiring board in a bare form and then at least partially sealed with a resin. A system may further include a second printed board which is independent from the first printed board and adhesively attached to a inner surface of the casing and connected to the first printed board by a flexible member. In addition the second circuit board may include structure which enables it to connect to an apparatus for programming an electronic component attached thereto.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: January 20, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Tsukada, Norio Nakamura, Minoru Nimura, Hiroyuki Suemori, Tomio Kamihata, Mutsuaki Yamazaki
  • Patent number: 5559109
    Abstract: A method of treating a PAF-mediated pathology or for treating or preventing psoriasis, nephritis, asthma, inflammation or shock by administering an effective amount of a PAF antagonist of the formula ##STR1## wherein R.sup.1 and R.sup.2 are each --R.sup.5, --CH.dbd.CH--R.sup.5 or --C.tbd.C--R.sup.5 ; R.sup.5 is an unsubstituted or substituted C.sub.6 -C.sub.14 carbocyclic aryl of an aromatic heterocyclic having from 5 to 14 ring atoms, of which from 1 to 5 are hetero-atoms selected from the group consisting of nitrogen, oxygen and sulfur, the heterocyclic group being unsubstituted or substituted; R.sup.3 is hydrogen, a C.sub.1 -C.sub.6 alkyl, cyano, or --R.sup.5 ; X is oxygen or sulfur; A is a 1,4-piperazin-1,4-diyl or a 1,4-homopiperazin-1,4-diyl; B is a C.sub.1 -C.sub.6 alkylene, carbonyl, thiocarbonyl, sulfinyl or sulfonyl; and R.sup.4 is an unsubstituted or substituted phenyl group.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: September 24, 1996
    Assignee: Sankko Company, Limited
    Inventors: Norio Nakamura, Nobuyuki Ohkawa, Takeshi Oshima, Masaaki Miyamoto, Yasuteru Iijima
  • Patent number: 5556852
    Abstract: Compounds of formula (I): ##STR1## wherein R.sup.1 and R.sup.2 is each --R.sup.5, --CH.dbd.CH--R.sup.5 or --C.tbd.C--R.sup.5, wherein R.sup.5 is optionally substituted aryl or aromatic heterocyclic; R.sup.3 is hydrogen, alkyl, cyano or --R.sup.5 ; X is oxygen or sulfur A is 1,4-piperazin-1,4-diyl or a 1,4-homopiperazin-1,4-diyl; B' is alkylene, carbonyl, thiocarbonyl, sulfinyl or sulfonyl: and R.sup.4 is optionally substituted phenyl and pharmaceutically acceptable salts thereof have valuable PAF antagonist activity.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: September 17, 1996
    Assignee: Sankyo Company, Limited
    Inventors: Norio Nakamura, Nobuyuki Ohkawa, Takeshi Oshima, Masaaki Miyamoto, Yasuteru Iijima