Patents by Inventor Norio Shoji
Norio Shoji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10587227Abstract: In an amplifier that uses a transistor, a minimum operation voltage is lowered. An amplifier includes a P-type transistor and an N-type transistor connected in series, and an operational amplifier. An output terminal of the operational amplifier is connected to gates of both the P-type transistor and the N-type transistor. One of an inverting input terminal and a non-inverting input terminal of the operational amplifier is connected to drains of both the P-type transistor and the N-type transistor. Further, a predetermined reference voltage is applied to another of the inverting input terminal and the non-inverting input terminal.Type: GrantFiled: February 3, 2016Date of Patent: March 10, 2020Assignee: Sony CorporationInventors: Hideyuki Takano, Fumitaka Kondo, Norio Shoji
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Publication number: 20190158032Abstract: In an amplifier that uses a transistor, a minimum operation voltage is lowered. An amplifier includes a P-type transistor and an N-type transistor connected in series, and an operational amplifier. An output terminal of the operational amplifier is connected to gates of both the P-type transistor and the N-type transistor. One of an inverting input terminal and a non-inverting input terminal of the operational amplifier is connected to drains of both the P-type transistor and the N-type transistor. Further, a predetermined reference voltage is applied to another of the inverting input terminal and the non-inverting input terminal.Type: ApplicationFiled: February 3, 2016Publication date: May 23, 2019Inventors: Hideyuki Takano, Fumitaka Kondo, Norio Shoji
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Patent number: 7259615Abstract: A bias-voltage supply circuit of a radio-frequency amplification circuit has the constant-voltage power supply generating a constant voltage higher than the bias voltage, a rectifier transistor and a constant-current power supply supplying a constant current to the rectifier transistor. The rectifier transistor is connected between a supply point of a bias voltage connected to an input terminal of the radio-frequency amplification transistor via an element for bias supply and a power supply voltage supply line, wherein a control terminal is kept by the constant voltage that the constant-voltage power supply generates. Since descent of the electric potential of the input terminal of a radio-frequency signal does not arise because of circuit composition, the radio-frequency amplification circuit has a good saturation characteristic.Type: GrantFiled: February 2, 2005Date of Patent: August 21, 2007Assignee: Sony CorporationInventors: Noboru Sasho, Norio Shoji
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Publication number: 20050179484Abstract: A bias voltage supply circuit of a radio-frequency amplification circuit has a constant-voltage power supply generating a constant voltage higher than the bias voltage, a rectifier transistor and a constant-current power supply supplying a constant current to the rectifier transistor. The rectifier transistor is connected between a supply point of a bias voltage connected to an input terminal of the radio-frequency amplification transistor via an element for bias supply and a power supply voltage supply line, wherein a control terminal is kept by a constant voltage that the constant-voltage power supply generates. Since descent of electric potential of the input terminal of a radio-frequency signal does not arise because of circuit composition, the radio-frequency amplification circuit has a saturation characteristic superior than a prior art.Type: ApplicationFiled: February 2, 2005Publication date: August 18, 2005Applicant: Sony CorporationInventors: Noboru Sasho, Norio Shoji
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Patent number: 6804074Abstract: A PLL circuit functioning as a clock recovery circuit in a tape recording and playback apparatus employing the PRML method has a level determining circuit for detecting that head output level (signal level) is at or lower than a certain level during track crossing for a high-speed search, and effects a hold on a loop filter according to a level determination output to thereby hold PLL operation, whereby the PLL behavior is not disturbed by a noise component occurring during track crossing. Thus, it is possible to stabilize search operation and increase the design margin.Type: GrantFiled: May 23, 2001Date of Patent: October 12, 2004Assignee: Sony CorporationInventors: Norio Shoji, Junkichi Sugita, Kimimasa Senba, Toshihiro Kawakubo
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Patent number: 6762894Abstract: A head apparatus which is tough against disturbing noise and superior in the S/N ratio and which can cope with an increase of the capacity of a recording medium is disclosed. A first playback amplifier for amplifying the playback signal of a MR head and a register circuit for setting the bias current to the MR head are formed as a COS IC. The COS IC is mounted on a suspension together with the MR head. A feeble playback signal outputted from the MR head is amplified by the first playback amplifier once and then transmitted to a mother IC over a pair of signal lines. The amplified playback signal is tough against disturbing noise during transmission.Type: GrantFiled: June 28, 2001Date of Patent: July 13, 2004Assignee: Sony CorporationInventors: Keiji Narusawa, Norio Shoji
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Patent number: 6693863Abstract: To provide an asymmetry correcting circuit capable of canceling an asymmetry simultaneously with quantization in an ADC and utilizing the dynamic range of the ADC effectively, and also to provide an information reproducing apparatus using such a correcting circuit.Type: GrantFiled: April 16, 2002Date of Patent: February 17, 2004Assignee: Sony CorporationInventors: Norio Shoji, Yuji Gendai, Kimimasa Senba, Nobuyoshi Kobayashi
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Patent number: 6683740Abstract: A write amplifier circuit in a magnetic storage system has a cross coupling circuit and an active damp circuit to supply an improved write current to the head writing the data onto the media within the magnetic storage system. The inclusion of the cross coupling circuit decreases a rise time and a fall time associated with the write current. The active damp circuit reduces the undershoot and ringing of the write current. Thus, the write amplifier circuit is suitable for high speed data storage writing applications requiring minimal distortion of the data written to a magnetic medium. The write amplifier circuit achieves these improvements in the waveform of the write current by incorporating circuit elements and using both a negative feedback path and a feedforward path.Type: GrantFiled: February 15, 2000Date of Patent: January 27, 2004Assignees: Sony Corporation, Sony Electronics, Inc.Inventors: Soon-Gil Jung, Shang-Ching Dong, Hiroshi Takeuchi, Norio Shoji, Keiji Narusawa, Michiya Sako
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Patent number: 6614304Abstract: The present invention relates to a variable gain circuit including: a first transistor and a second transistor each having a control electrode connected to a circuit input terminal; a load connected between a first power supply and a first electrode of at least one of the first transistor and the second transistor; a third transistor and a fourth transistor having second electrodes connected to the first transistor and the second transistor, respectively, and each having a first electrode and a control electrode connected to each other; a first variable current source connected between a second power supply and the second electrodes of the first transistor and the third transistor and having a current value variable according to an external control signal; a second variable current source connected between the second power supply and the second electrodes of the second transistor and the fourth transistor and having a current value variable according to the control signal; a current source connected between tType: GrantFiled: January 4, 2002Date of Patent: September 2, 2003Assignee: Sony CorporationInventors: Norio Shoji, Tatsuya Shirakawa
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Patent number: 6597650Abstract: A nonlinearity compensation circuit is disclosed which includes an inverse hyperbolic function generation circuit for converting differential currents corresponding to input signals in+ and in− into differential voltages which increase in proportion to an inverse hyperbolic function, an offset provision circuit for providing an offset corresponding to control signals c+ and c− to the differential voltages outputted from the inverse hyperbolic function generation circuit and a hyperbolic function generation circuit for converting the differential voltages to which the offset has been provided by the offset provision circuit into signals which increase in proportion to a hyperbolic function and outputting the resulting signals as output signals out+ and out−. Consequently, compensation for the nonlinearity such as second order distortion can be performed for the read signal from a recording medium.Type: GrantFiled: June 1, 2001Date of Patent: July 22, 2003Assignee: Sony CorporationInventors: Masayuki Katakura, Junkichi Sugita, Norio Shoji, Masato Sekine, Kimimasa Senba, Katsuhisa Daio
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Patent number: 6496076Abstract: A PLL (phase-locked loop) circuit is configured with a phase-error detection circuit comprises the following: a provisional judge circuit for provisionally judging a data signal being input to an A/D converter into three levels of 1, 0, and −1; a pattern detector which, among data signals being input in accordance with a result of the provisional judgment, checks a transition pattern ranging from a data signal that precedes one clock cycle to the actually present data signal, and then, when a specific pattern is detected, instructs a selector to select output data from the A/D converter; and the selector which, in compliance with instruction from the pattern detector, selects phase-error data from data signals output from the A/D converter, and then converts the selected phase-error data into an electric current before externally delivering it as an error-current.Type: GrantFiled: November 22, 2000Date of Patent: December 17, 2002Assignee: Sony CorporationInventors: Norio Shoji, Kimimasa Senba
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Publication number: 20020172112Abstract: To provide an asymmetry correcting circuit capable of canceling an asymmetry simultaneously with quantization in an ADC and utilizing the dynamic range of the ADC effectively, and also to provide an information reproducing apparatus using such a correcting circuit.Type: ApplicationFiled: April 16, 2002Publication date: November 21, 2002Inventors: Norio Shoji, Yuji Gendai, Kimimasa Senba, Nobuyoshi Kobayashi
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Publication number: 20020130718Abstract: The present invention relates to a variable gain circuit including: a first transistor and a second transistor each having a control electrode connected to a circuit input terminal; a load connected between a first power supply and a first electrode of at least one of the first transistor and the second transistor; a third transistor and a fourth transistor having second electrodes connected to the first transistor and the second transistor, respectively, and each having a first electrode and a control electrode connected to each other; a first variable current source connected between a second power supply and the second electrodes of the first transistor and the third transistor, and having a current value variable according to an external control signal; a second variable current source connected between the second power supply and the second electrodes of the second transistor and the fourth transistor, and having a current value variable according to the control signal; a current source connected betweenType: ApplicationFiled: January 4, 2002Publication date: September 19, 2002Inventors: Norio Shoji, Tatsuya Shirakawa
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Patent number: 6400184Abstract: A transistor output circuit featuring a low power consumption, high speed and stabilized operation is realized.Type: GrantFiled: January 22, 2001Date of Patent: June 4, 2002Assignee: Sony CorporationInventors: Norio Shoji, Hideyuki Nishioka
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Publication number: 20020053935Abstract: A nonlinearity compensation circuit is disclosed which includes an inverse hyperbolic function generation circuit for converting differential currents corresponding to input signals in+ and in− into differential voltages which increase in proportion to an inverse hyperbolic function, an offset provision circuit for providing an offset corresponding to control signals c+ and c− to the differential voltages outputted from the inverse hyperbolic function generation circuit and a hyperbolic function generation circuit for converting the differential voltages to which the offset has been provided by the offset provision circuit into signals which increase in proportion to a hyperbolic function and outputting the resulting signals as output signals out+ and out−. Consequently, compensation for the nonlinearity such as second order distortion can be performed for the read signal from a recording medium.Type: ApplicationFiled: June 1, 2001Publication date: May 9, 2002Inventors: Masayuki Katakura, Junkichi Sugita, Norio Shoji, Masato Sekine, Kimimasa Senba, Katsuhisa Daio
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Publication number: 20020017934Abstract: A PLL circuit functioning as a clock recovery circuit in a tape recording and playback apparatus employing the PRYL method has a level determining circuit for detecting that head output level (signal level) is at or lower than a certain level during track crossing for a high-speed search, and effects a hold on a loop filter according to a level determination output to thereby hold PLL operation, whereby the PLL behavior is not disturbed by a noise component occurring during track crossing. Thus, it is possible to stabilize search operation and increase the design margin.Type: ApplicationFiled: May 23, 2001Publication date: February 14, 2002Inventors: Norio Shoji, Junkichi Sugita, Kimimasa Senba, Toshihiro Kawakubo
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Publication number: 20020001149Abstract: A head apparatus is disclosed which is tough against disturbing noise and superior in the S/N ratio and can cope with an increase of the capacity of a recording medium. A first playback amplifier for amplifying a playback signal of an MR head and a register circuit for setting a bias current to the MR head are formed as a COS IC. The COS IC is mounted on a suspension together with the MR head. A feeble playback signal outputted from the MR head is amplified by the first playback amplifier once and then transmitted to a mother IC over a pair of signal lines. The amplified playback signal is tough against disturbing noise during transmission.Type: ApplicationFiled: June 28, 2001Publication date: January 3, 2002Applicant: Sony CorporationInventors: Keiji Narusawa, Norio Shoji
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Patent number: 6154333Abstract: An amplification circuit for an MR head which can realize a reduction of the power consumption, simplification of the circuit configuration by providing capacitors inside the circuit, and reduction of the number of externally provided parts, wherein a current is supplied to an MR head resistor from a bias current source and the amount of change of the head resistance is converted to a voltage change when reproducing magnetically recorded data. A direct current component of the voltage dropped in the head resistor is cut by capacitors, and only the alternating current component is input to a differential amplification circuit configured by transistors. Recorded data can be distinguished in accordance with an amplified output voltage, so capacitances of direct current cut-off capacitors can be set small and thus the direct current cut-off capacitors can be provided in the IC chip and the number of external parts can be reduced.Type: GrantFiled: December 17, 1998Date of Patent: November 28, 2000Assignee: Sony CorporationInventors: Keiji Narusawa, Norio Shoji
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Patent number: 6075394Abstract: In a PLL circuit, the phase of the frequency of an input signal is compared with that of an oscillation frequency generated from a voltage-controlled oscillator. Charge pump circuits are provided which outputs currents pulse-width modulated based on information about the error between the two phases, respectively. An output voltage of a capacitor provided at a stage subsequent to one of the charge pump circuits is converted into a current by a gm amplifier. Further, the converted current is added to an output current of the other charge pump circuit. The so-added output is used as a control input for the voltage-controlled oscillator. The oscillation frequency of the voltage-controlled oscillator is produced as an output signal frequency.Type: GrantFiled: September 29, 1998Date of Patent: June 13, 2000Assignee: Sony CorporationInventor: Norio Shoji
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Patent number: 5940952Abstract: A method for applying a corrosion-protective coating, with a heat-shrinkable tube, to a joint between welded end portions of corrosion-protectively coated steel pipes, has a configuration comprising the steps of: preparing a coating implement having a releasant layer formed on the outer circumferential portion of the heat-shrinkable tube, and a heating layer formed on the outer circumferential portion of the releasant layer; positioning the coating implement so as to cover the welded portion of the joint and its adjacent portions; thermally shrinking the coating implement in a state in which the gap between the coating implement and the aforementioned portions is kept in a vacuum; and removing the releasant layer and the heating layer, whereby the aforementioned portions are corrosion-protectively coated by the heat shrinkage of the tube.Type: GrantFiled: October 11, 1996Date of Patent: August 24, 1999Assignees: Nitto Denko Corporation, Nippon Kokan Co., Ltd., Nippon Kokan Koji Kabushiki Kaisha KanagawaInventors: Ryouichi Ikeda, Minoru Komura, Yoshihiro Okano, Norio Shoji, Toshiyuki Namioka, Akio Kida, Kiyotaka Hirahara