Patents by Inventor Noritaka Anzai

Noritaka Anzai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6833607
    Abstract: A resin-molded semiconductor device capable of preventing an adhesive from flowing out along conductive paths from where electronic parts are attached on the conductive paths when the electronic parts are fixed to the conductive paths of a semiconductor package. The semiconductor device comprises a semiconductor chip (10), a plurality of conductive paths (12) connected to the semiconductor chip through conductive wires (11) extending from said chip, and an electronic part (13) mounted in such a manner as to electrically connect to two pieces of the conductive paths through the intermediary of an adhesive showing fluidity before hardening and molded in one body the semiconductor chip. In the conductive path, a raised portion is provided to prevent the adhesive from flowing out along the conductive path in the longitudinal direction of the conductive path before the adhesive hardens.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: December 21, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Noritaka Anzai, Makoto Terui
  • Publication number: 20040238929
    Abstract: In a semiconductor device having a WCSP type construction package, to increase inductance without increasing further an area conventionally occupied by a coil. A pseudo-post part 27 comprising a magnetic body is extended in a direction perpendicular to a main surface 12a of a semiconductor chip 12, on a second insulating layer 21 of a WCSP 10. A first conductive part 15a and a second conductive part 15b constructed as square frames are respectively provided so as to surround the pseudo-post part, on respective top surfaces of a second insulation layer and a third insulating layer 22 which are separated parallel to each other, in an extension direction of the pseudo-post part. A coil 100 being a substantially spiral shape conductive path is formed from, the first conductive part, the second conductive part, and a connection part 26 which electrically connects the one ends of the first and second conductive parts.
    Type: Application
    Filed: May 26, 2004
    Publication date: December 2, 2004
    Inventors: Noritaka Anzai, Makoto Terui
  • Patent number: 6806564
    Abstract: A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: October 19, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Makoto Terui, Noritaka Anzai
  • Publication number: 20040145041
    Abstract: A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.
    Type: Application
    Filed: January 15, 2004
    Publication date: July 29, 2004
    Inventors: Makoto Terui, Noritaka Anzai
  • Patent number: 6707146
    Abstract: A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: March 16, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Makoto Terui, Noritaka Anzai
  • Publication number: 20040026782
    Abstract: A semiconductor device includes a semiconductor chip, electrodes pads, insulating layer, first and second conductive patterns and external terminals. The electrode pads are formed on a first area of a main surface of the semiconductor chip. The insulating layer is formed on a second area of the semiconductor chip so as to expose the electrode pads. The first conductive patterns provides a ground potential and is formed on the insulating layer. The second conductive pattern transfers a signal. The second conductive pattern and is formed on the insulating layer and located between the first conductive patterns. The external terminals are formed on the first and second patterns at the second area.
    Type: Application
    Filed: August 1, 2003
    Publication date: February 12, 2004
    Inventor: Noritaka Anzai
  • Publication number: 20030205808
    Abstract: A semiconductor device that includes a semiconductor substrate having a main surface, the main surface including a first area formed with a high-frequency circuit element and a second area located around the first area and formed with a low-frequency circuit element. The semi-conductor device also includes a sealing resin which covers the main surface; a plurality of first external terminals which are formed above the second area and which are electrically connected to the high-frequency circuit element, the first external terminals protruding from the surface of the sealing resin. The semiconductor device further includes a plurality of second external terminals which are formed above the second area and which are electrically connected to the low-frequency circuit element, the second external terminals protruding from the surface of the sealing resin.
    Type: Application
    Filed: April 21, 2003
    Publication date: November 6, 2003
    Inventors: Makoto Terui, Noritaka Anzai, Hiroyuki Mori
  • Publication number: 20030189251
    Abstract: A semiconductor device that includes a semiconductor substrate having a main surface, the main surface including a first area formed with a high-frequency circuit element and a second area located around the first area and formed with a low-frequency circuit element. The semiconductor device also includes a sealing resin which covers the main surface; a plurality of first external terminals which are formed above the second area and which are electrically connected to the high-frequency circuit element, the first external terminals protruding from the surface of the sealing resin. The semiconductor device further includes a plurality of second external terminals which are formed above the second area and which are electrically connected to the low-frequency circuit element, the second external terminals protruding from the surface of the sealing resin.
    Type: Application
    Filed: November 7, 2002
    Publication date: October 9, 2003
    Inventors: Makoto Terui, Noritaka Anzai, Hiroyuki Mori
  • Patent number: 6608375
    Abstract: A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: August 19, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Makoto Terui, Noritaka Anzai
  • Publication number: 20030102543
    Abstract: A resin-molded semiconductor device capable of preventing an adhesive from flowing out along conductive paths from where electronic parts are attached on the conductive paths when the electronic parts are fixed to the conductive paths of a semiconductor package. The semiconductor device comprises a semiconductor chip (10), a plurality of conductive paths (12) connected to the semiconductor chip through conductive wires (11) extending from said chip, and an electronic part (13) mounted in such a manner as to electrically connect to two pieces of the conductive paths through the intermediary of an adhesive showing fluidity before hardening and molded in one body the semiconductor chip. In the conductive path, a raised portion is provided to prevent the adhesive from flowing out along the conductive path in the longitudinal direction of the conductive path before the adhesive hardens.
    Type: Application
    Filed: April 19, 2002
    Publication date: June 5, 2003
    Inventors: Noritaka Anzai, Makoto Terui
  • Patent number: 6541306
    Abstract: A resin-sealed semiconductor device according to this invention is an LOC type semiconductor device comprising a semiconductor chip having a circuit surface on which an electrode is formed; a lead which is arranged in such a manner that the distal end of the lead overlaps the semiconductor chip, and which is electrically connected to each electrode; a lead fixing resin layer interposed between the semiconductor chip and the lead to fix them; and a sealing resin layer coated to cover the semiconductor chip and the lead. The diameter of filler contained in the lead fixing resin layer is about 1/10 to 1/5 the diameter of filler contained in the sealing resin layer, and is about 1/10 a gap between the lead and the semiconductor chip.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: April 1, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Noritaka Anzai
  • Publication number: 20020195705
    Abstract: A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.
    Type: Application
    Filed: August 5, 2002
    Publication date: December 26, 2002
    Inventors: Makoto Terui, Noritaka Anzai
  • Publication number: 20020145180
    Abstract: A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.
    Type: Application
    Filed: April 6, 2001
    Publication date: October 10, 2002
    Inventors: Makoto Terui, Noritaka Anzai
  • Publication number: 20020000676
    Abstract: A resin-sealed semiconductor device according to this invention is an LOC type semiconductor device comprising a semiconductor chip having a circuit surface on which an electrode is formed; a lead which is arranged in such a manner that the distal end of the lead overlaps the semiconductor chip, and which is electrically connected to each electrode; a lead fixing resin layer interposed between the semiconductor chip and the lead to fix them; and a sealing resin layer coated to cover the semiconductor chip and the lead. The diameter of filler contained in the lead fixing resin layer is about {fraction (1/10)} to ⅕ the diameter of filler contained in the sealing resin layer, and is about {fraction (1/10)} a gap between the lead and the semiconductor chip.
    Type: Application
    Filed: June 7, 2001
    Publication date: January 3, 2002
    Inventors: Shinji Ohuchi, Noritaka Anzai
  • Patent number: 6323551
    Abstract: On a semiconductor element in the which a circuit pattern and electrodes are formed on a circuit forming surface, a plurality of leads, which are formed by a strip-shaped metal piece having a rectangular exposed portion, are disposed in parallel at predetermined intervals and are electrically connected to each of the electrodes. Molding is effected by a resin so as to cover portions of the plurality of leads other than the exposed portions and to cover the circuit forming surface and side surfaces of the semiconductor element. Flux for soldering is applied to at least one of spherical solders and the exposed portions. The spherical solder is disposed one by one on each of the exposed portions so as to form a zigzag in a direction in which the plurality of leads are arranged. The solder is heated and melted such that the solder bump which covers the entire surface of the rectangular exposed portion is formed by the melted solder.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: November 27, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Noritaka Anzai
  • Patent number: 6274938
    Abstract: A resin-sealed LOC type semiconductor device includes semiconductor chip having a circuit surface on which electrodes are formed. Leads are arranged with their distal ends overlapping the semiconductor chip, electrically connected to the respective electrodes. A lead fixing resin layer is interposed between the semiconductor chip and the leads to fix them. A sealing resin layer coats the semiconductor chip and the lead to over them. The diameter of filler contained in the lead fixing resin layer is about {fraction (1/10)} to ⅕ the diameter of filler contained in the sealing resin layer, and is about {fraction (1/10)} the width of a gap between each lead and the semi conductor chip.
    Type: Grant
    Filed: September 9, 1998
    Date of Patent: August 14, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Noritaka Anzai
  • Patent number: 6259163
    Abstract: A metal pattern 4 is formed at a rear surface of a substrate 3 at a front surface of which a molded semiconductor chip is mounted, the metal pattern 4 is covered with an insulating film 5 except at its connecting area 4a and a solder ball 6 is bonded to the connecting area 4a. The area of the metal pattern 4 other than the connecting area 4a inclines toward the substrate 3 and gradually becomes thinner toward the outside. Stress, which is applied to the solder ball 6, is imparted in a diagonal direction and is dispersed. As a result, the number of occurrences of cracks X is reduced and the solder ball which is used to achieve connection with an external substrate is effectively prevented from becoming electrically disconnected.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: July 10, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Yoshimi Egawa, Noritaka Anzai
  • Patent number: 6251704
    Abstract: A metal is formed at a rear surface of a substrate, the substrate also having a front surface at which a molded semiconductor chip is mounted. The metal pattern is covered with an insulating film, except for at a connecting area. A solder ball is bonded to the connecting area. The area of the metal pattern other than the connecting area inclines toward the substrate and gradually becomes thinner toward the outside thereof. Stress, which is applied to the solder ball, is imparted in a diagonal direction and is dispersed. As a result, the number of occurrences of cracks is reduced, and the solder ball which is used to achieve connection with an external substrate, is effectively prevented form becoming electrically disconnected.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: June 26, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Yoshimi Egawa, Noritaka Anzai
  • Patent number: 6204563
    Abstract: A semiconductor device for mounting on an external substrate includes a semiconductor chip, a high thermal elastic internal substrate and a high elastic liquid resin. The semiconductor chip has bump electrodes formed on its main surface. The high thermal elastic internal substrate includes a conductive pattern on one surface and external electrodes on the other surface. The conductive pattern is electrically connected to the bump electrodes. The external electrodes are electrically connected to the conductive pattern and mounted on the external substrate. The high elastic liquid resin covers the surface of the semiconductor chip, the one surface of the internal substrate and the bump electrodes. The internal substrate has a Young modulus of about 8000 to 15000 kg/mm2, which is larger than a Young modulus of the external substrate.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: March 20, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Noritaka Anzai, Yoshimi Egawa
  • Patent number: 5999413
    Abstract: A resin sealing type semiconductor device capable of making a resin burr hard to occur when formed by molds and of restraining cracks in solder, is actualized by providing a stepped portion on a resin sealing body for covering a circuit forming surface of a semiconductor chip, making leads exposed from this exposed surface and joining solder bumps to the leads.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: December 7, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Noritaka Anzai