Abstract: According to one embodiment, a semiconductor memory device includes a housing and terminals. The housing has a first end edge extending in a first direction and a second end edge opposite to the first end edge. The terminals include signal terminals and include first terminals, second terminals, and third terminals. The first terminals are arranged in the first direction at a position close to the first end edge. The second terminals are arranged in the first direction with intervals at a position closer to the first end edge than the second end edge. The first plurality of terminals are closer to the first end edge than the second plurality of terminals are. The third terminals are arranged in the first direction with intervals at a position closer to the second end edge than the first end edge.

Abstract: According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

Abstract: According to one embodiment, a semiconductor memory device includes a housing and terminals. The housing has a first end edge extending in a first direction and a second end edge opposite to the first end edge. The terminals include signal terminals and include first terminals, second terminals, and third terminals. The first terminals are arranged in the first direction at a position close to the first end edge. The second terminals are arranged in the first direction with intervals at a position closer to the first end edge than the second end edge. The first plurality of terminals are closer to the first end edge than the second plurality of terminals are. The third terminals are arranged in the first direction with intervals at a position closer to the second end edge than the first end edge.

Abstract: According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

Abstract: According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

Abstract: A memory card includes a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, wherein N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, wherein K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

Abstract: According to one embodiment, a semiconductor memory device includes a housing and terminals. The housing has a first end edge extending in a first direction and a second end edge opposite to the first end edge. The terminals include signal terminals and include first terminals, second terminals, and third terminals. The first terminals are arranged in the first direction at a position close to the first end edge. The second terminals are arranged in the first direction with intervals at a position closer to the first end edge than the second end edge. The first plurality of terminals are closer to the first end edge than the second plurality of terminals are. The third terminals are arranged in the first direction with intervals at a position closer to the second end edge than the first end edge.

Abstract: A memory card includes a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, wherein N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, wherein K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

Abstract: According to an embodiment, a tuner unit, a managing unit, a private code verifying unit, an application origin verifying unit, and a device operation command processing unit. The tuner unit is configured to perform a decoding process of a broadcast program and program related information from broadcasting waves. The managing unit is configured to store a private code on a device-by-device basis. The private code verifying unit is configured to verify whether the private code obtained from an information manipulation device matches with the stored private code. The application origin verifying unit is configured to determine whether first origin information that has been received matches with second origin information of the application being executed. The device operation command processing unit is configured to allow execution of the device operation command when the first origin information and the second origin information match and when the private codes match.

Abstract: In at least one embodiment, a reception apparatus includes a discrimination data receiver configured to receive discrimination data that is transmitted from outside the reception apparatus and that has been associated with display information to be displayed; and an output controller configured to control output of the display information to two or more display screens according to the discrimination data.

Abstract: According to an embodiment, a tuner unit, a managing unit, a private code verifying unit, an application origin verifying unit, and a device operation command processing unit. The tuner unit is configured to perform a decoding process of a broadcast program and program related information from broadcasting waves. The managing unit is configured to store a private code on a device-by-device basis. The private code verifying unit is configured to verify whether the private code obtained from an information manipulation device matches with the stored private code. The application origin verifying unit is configured to determine whether first origin information that has been received matches with second origin information of the application being executed. The device operation command processing unit is configured to allow execution of the device operation command when the first origin information and the second origin information match and when the private codes match.

Abstract: An information output apparatus has a first interface to receive an equipment operational signal from a short-range wireless communication apparatus, a second interface to receive broadcast wave data based on the equipment operational signal, a third interface to transmit the equipment operational signal to an information generating apparatus, a fourth interface to receive video data transmitted from the information generating apparatus, a fifth interface to receive a control command transmitted from the information generating apparatus in response to the equipment operational signal transmitted from the third interface part, an information superimposing part to transmit the equipment operational signal from the third interface part to the information generating apparatus and then to superimpose video data updated by the information generating apparatus and received from the fourth interface part with the broadcast wave data to display the superimposed data on a display part.

Abstract: In at least one embodiment, a reception apparatus includes a discrimination data receiver configured to receive discrimination data that is transmitted from outside the reception apparatus and that has been associated with display information to be displayed; and an output controller configured to control output of the display information to two or more display screens according to the discrimination data.

Abstract: An information output apparatus has a first interface to receive an equipment operational signal from a short-range wireless communication apparatus, a second interface to receive broadcast wave data based on the equipment operational signal, a third interface to transmit the equipment operational signal to an information generating apparatus, a fourth interface to receive video data transmitted from the information generating apparatus, a fifth interface to receive a control command transmitted from the information generating apparatus in response to the equipment operational signal transmitted from the third interface part, an information superimposing part to transmit the equipment operational signal from the third interface part to the information generating apparatus and then to superimpose video data updated by the information generating apparatus and received from the fourth interface part with the broadcast wave data to display the superimposed data on a display part.

Abstract: An information receiver includes: a communication module that is configured to receive, over a network, information from a first apparatus that uses an internet protocol of a first version as a communication protocol and a second apparatus that uses an internet protocol of a second version as a communication protocol; and a storage module that stores names of the first apparatus and the second apparatus from which the communication module has received information, each of the names being correlated with the internet protocol of one of the first version and the second version being used when the respective names are received, wherein the communication module receives information from the first apparatus or the second apparatus using the internet protocol of the first version or second version by referring to the names and the internet protocol being correlated therewith stored in the storage module.

Abstract: Disclosed is an FEC encoding method, including: sequentially storing payloads each included in sequentially supplied media packets into a buffer memory; detecting whether number of the payloads stored reaches a prescribed number or whether a period of time since the payloads have started to be stored into the buffer memory reaches a certain period of time; when detecting that the number of the payloads reaches the prescribed number, performing FEC operation using the prescribed number of payloads stored to generate first information for FEC; when detecting that the period of time since the payloads have started to be stored into the buffer memory reaches the certain period of time, performing FEC operation using the payloads stored into the buffer memory to generate second information for FEC; and outputting the first and second information together with the media packets corresponding thereto.

Abstract: A receiver for the digital broadcasts with which an appropriate copy regulation is executed for a temporal recording. Regarding the temporal recording of the programs of the digital broadcasts, either of the signals of the system including at least the signals, which represent “recording permitted” or “recording prohibited”, is received as the temporal record control data and the record control is executed in accordance with the temporal record control data to execute the temporal recording of the received broadcast program or not to execute the temporal recording.

Abstract: According to one embodiment, a broadcast recording apparatus has a tuner unit which receives a broadcast signal, demodulates the received signal, and outputs video image and voice signals, first and second hard disk drive units which record the video image and voice signals from the tuner unit in a memory region, and a control unit which controls the first and second hard disk drive units to record the video image and voice signals in each one of a first storage memory region of the first hard disk drive unit and a second storage memory region of the second hard disk drive unit.

Abstract: According to one embodiment, an MPEG2-TTS is generated by adding time stamps to each packet in an MPEG2-TS (step ST41) and the MPEG2-TTS is transmitted to a communication channel (the Internet, etc.) (step ST45). At this time, if null packets are included in an original MPEG2-TS, all null packets are removed from the MPEG2-TTS before it is transmitted. Thereby, an averaged rate of data transfer is decreased. Since each packet in the MPEG2-TTS has a time stamp, each packet can be decoded at original timing then synchronization of broadcasting times between a transmission and a reception is secured.

Abstract: According to one embodiment, a video communication apparatus comprising communication unit which performs communication with an external device, tuner unit which receives broadcasting signals, first codec and second codec which receive and decode video/audio signals and output the decoded signals, display unit which receives the decoded signals, and control unit which controls so as, when one of the codecs is designated and an instruction to perform video communications with the external device is received, or, one of the codecs is designated and an instruction to perform a process of decoding video/audio signals of broadcasting signals, to perform the instructed process by the designated codec, and when the designated codec is already being used, to perform the instructed process by use of the codec that is not being used, and display message to the effect that the other codec is being used.