Abstract: A demultiplexing/GOP head detecting section detects a PCR value, while a recording/reproduction control section records a video or audio packet in a bit stream file and records information on the number of packets every PCR value and GOP. In reproduction, a reproduction position corresponding to a shift time is judged on the basis of information on the number of packets at every PCR value and GOP. This improves the shifting and returning speeds to time shift reproduction.

Abstract: A demultiplexing/GOP head detecting section detects a PCR value, while a recording/reproduction control section records a video or audio packet in a bit stream file and records information on the number of packets every PCR value and GOP. In reproduction, a reproduction position corresponding to a shift time is judged on the basis of information on the number of packets at every PCR value and GOP. This improves the shifting and returning speeds to time shift reproduction.

Abstract: A digital broadcast recording/reproducing apparatus which is able to determine the bit rate at the time of recording operation in accordance with the bit rate of the recorded video data and audio data, so that the bit rate at the time of reproducing operation is reduced lower than the bit rate at the time of recording operation is obtained. When reserving the reproduction bit rate, it prevents taking a large band superfluously. The amount of records and time for every picture which are the coding unit of the video signal of MPEG-2 are held at the time of recording operation, and the bit rate for every picture is calculated from these data. The value somewhat higher than the maximum or maximum as the reproduction bit rate is set up, and it reproduces.

Abstract: A digital broadcast receiving device includes a first processor for extracting added information, a storage device for storing the added information, and a second processor having a low power consumption mode and a normal power mode, for effecting the circuit control for the watching and listening operation according to a preset program and the added information. The first processor informs the second processor that the added information is extracted, the second processor changes the mode thereof to the normal power mode when it is informed from the first processor that the added information is extracted while it is set in the low power consumption mode in the standby state, writes the added information extracted by the first processor into the storage device, and changes the mode thereof into the low power consumption mode after completion of the write operation.

Abstract: A receiver for the digital broadcasts with which an appropriate copy regulation is executed for a temporal recording. Regarding the temporal recording of the programs of the digital broadcasts, either of the signals of the system including at least the signals, which represent “recording permitted” or “recording prohibited”, is received as the temporal record control data and the record control is executed in accordance with the temporal record control data to execute the temporal recording of the received broadcast program or not to execute the temporal recording.

Abstract: Digital broadcast receiving terminal apparatus which receives multi-channel digital broadcast signals to record the huge capacity without deteriorating the quality of signals and to visualize the digital broadcasting. The outputs form the error correction decoding circus 4 are applied to the TS processor 12 via the switches SW 1 and SW 2, at the same time they are applied to the recording program selector 11. The recording program selector 11 applies the encoded data of the predetermined program to the digital interface 13, the digital interface 13 inputs and outputs the encoded data through bus in the IEEE1394 specification for example. Thus, the encoded data are applied to the external equipment and recorded as they are, and the degradation of the quality can be prevented. The switches SW 1 and SW 2 changes the receiving signals and the outputs from the digital interface 13 and applies them to the TS processor 12. The TS processor 12 depacketizes the input encoded data.

Abstract: Video signals are encrypted so that only the privileged viewers can watch them. A layer coding unit divides video signals into two layers and encodes each layer. An encrypting unit encrypts the low-quality layer data items according to the setting signal from a secret level setting unit and supplies the encrypted signal to a combining unit. Another encrypting unit encrypts the high-quality layer data items according to the setting signal from a secret level setting unit and supplies the encrypted signal to the combining unit. Ideally the high-quality layer data items are encrypted at a secret level that is higher than the secret level used to encrypt the low-quality layer data items. The synthesized data from the combining unit is converted at a communication modem into communication data, which is transmitted to a reception apparatus.

Abstract: A PLL circuit for use in a digital broadcasting receiver includes a receiver for receiving a bit stream containing program clock references (PCRs) transmitted from a broadcast station. The PCRs correspond to a frequency and phase of a transmitter system clock. The circuit also contains an oscillator for generating receiver system clocks, a counter responsive to the system clocks, and a connection to allow the bit stream to flow from the receiver to the oscillator. A controller controls the counter based on differences between the PCRs in the bit stream and the counter output. A load control means successively loads the PCRs on the counter in their order of transmission to lock the frequency and phase of the receiver system clock provided from the oscillator with the frequency and phase of the transmitter system clock.

Abstract: A system capable of performing compatible transmitting and receiving processes, regardless of whether a TV signal on the transmission side is a high-resolution signal or a low-resolution signal or whether the reception side includes a high-resolution display unit or a low-resolution display unit. On the transmission side, a frequency division circuit divides a high-resolution TV signal into signals in a plurality of frequency bands. The signals in each frequency band are converted into signals of a horizontal and vertical low band (a low-resolution TV signal band). The converted signals are coded by coding units, which transmit the coded signals. On the reception side, the coded signals multiplexed on the transmission side are separated and decoded at decoding units. A frequency synthesizing circuit restores the frequency bands of the decoded signals to the original bands. Then, the resulting signals are displayed with a high resolution. A low-resolution signal is coded and then transmitted.

Abstract: A main signal as the existing television signal and a helper signal for high definition are prepared in a transmitter. The energy of the main signal for a plurality of pixels is sequentially detected by an energy detector constituted by an absolute value circuit and an accumulator. The helper signal is controlled by a level controller, constituted by an adder and a divider, in such a way that its level follows according to the level of the detected energy. The level-controlled helper signal is frequency-multiplexed with the main signal having a frequency band of a removed region by a frequency multiplexer. A frequency-multiplexed signal separator of a receiver separates the mutiplexed signal into the main signal and the helper signal. The energy of the separated main signal for a plurality of pixels is sequentially detected by an energy detector constituted by an absolute value circuit and an accumulator.

Abstract: An address control circuit for a video memory of a multi-image display system. The circuit includes a video signal source, a video memory for storing the video signal, an address holding circuit for controlling write addresses of the video memory which outputs address values during a video image period and holds address value corresponding to a start instance of a blanking period during the blanking period and a bias generating circuit for positioning address areas of the video memory in which the video signal is stored.

Abstract: A noninterlaced Y signal is separated into a horizontal high frequency component H and a horizontal low frequency component L by a LPF and an adder circuit at a time of interlace conversion. The component H is converted to an interlaced signal by a field repeating process comprising an interfield averaging process by an interfield averaging circuit, a field thinning out process by a field thinning out circuit and a delay process by an interlace conversion circuit. On the other hand, the component L is converted to an interlaced signal by a line thinning out process by an interlace conversion circuit. At a time of noninterlace conversion, the interlaced Y signal is separated into the components H and L by an LPF and an adder circuit.