Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a first memory cell, a first word line, a first circuit coupled to the first word line, a first driver used for a write operation and a read operation, a second driver used for an erase operation, and a voltage generator. The first circuit includes: a second circuit capable of electrically coupling the first word line and a first interconnect; a third circuit capable of electrically coupling the first interconnect and a second interconnect; a fourth circuit capable of electrically coupling the second interconnect and the first driver in the write and read operations; and a fifth circuit capable of electrically coupling the second interconnect and the second driver in the erase operation.

Abstract: A semiconductor memory device includes a plurality of blocks of memory cells, including first, second, and third blocks of a first group of blocks and fourth fifth and sixth blocks of a second group of blocks, a plurality of word lines for each of the blocks, a first decode circuit for the first group, and a second decode circuit for the second group. When the first block is selected, the first decode circuit transfers a first voltage to the word lines of the first block, transfers a second voltage lower than the first voltage to the word lines of the second block, and causes the word lines of the third block to go into an electrically floating state, and the second decode circuit causes the words lines of the fourth block, the fifth block, and the sixth block into the electrically floating state.

Abstract: A semiconductor memory device includes a plurality of blocks of memory cells, including first, second, and third blocks of a first group of blocks and fourth fifth and sixth blocks of a second group of blocks, a plurality of word lines for each of the blocks, a first decode circuit for the first group, and a second decode circuit for the second group. When the first block is selected, the first decode circuit transfers a first voltage to the word lines of the first block, transfers a second voltage lower than the first voltage to the word lines of the second block, and causes the word lines of the third block to go into an electrically floating state, and the second decode circuit causes the words lines of the fourth block, the fifth block, and the sixth block into the electrically floating state.

Abstract: A semiconductor storage device according to the present embodiment includes a memory cell array including a plurality of memory cells. A plurality of word lines are electrically connected to control gates of the memory cells. A plurality of bit lines are electrically connected to one end of a current path of the memory cells. A sense amplifier part detects data stored in the selected memory cells. A power supply part converts an external power supply voltage to an internal power supply voltage and supplies the internal power supply voltage to the sense amplifier part. A power supply wire extends above the memory cell array and is provided to range from the power supply part to the sense amplifier part.

Abstract: A semiconductor device includes an input-part receiving a first voltage and an output-part outputing a second voltage. A current mirror part receives the first voltage. A reference voltage is supplied to a gate of a reference transistor. The reference transistor is electrically connected between the current-mirror part and a ground voltage. A monitor transistor includes a gate electrically connected to the second power-supply voltage, and is electrically connected between the current-mirror part and the ground voltage. A voltage-generation transistor includes a gate electrically connected to both the current-mirror part and the reference transistor. The voltage-generation transistor is electrically connected between the input-part and the output-part. A first capacitor including one end electrically connected to the output-part, and the other end electrically connected to both the current-mirror part and the reference transistor.

Abstract: A semiconductor device includes an input-part receiving a first voltage and an output-part outputing a second voltage. A current mirror part receives the first voltage. A reference voltage is supplied to a gate of a reference transistor. The reference transistor is electrically connected between the current-mirror part and a ground voltage. A monitor transistor includes a gate electrically connected to the second power-supply voltage, and is electrically connected between the current-mirror part and the ground voltage. A voltage-generation transistor includes a gate electrically connected to both the current-mirror part and the reference transistor. The voltage-generation transistor is electrically connected between the input-part and the output-part. A first capacitor including one end electrically connected to the output-part, and the other end electrically connected to both the current-mirror part and the reference transistor.

Abstract: A voltage generating circuit includes first and second step-up circuits, each having first and second input terminals and an output terminal and configured to increase a voltage level of an input signal supplied through the first input terminal and output the signal with the increased voltage level through the output terminal. The second input terminal of the first step-up circuit is connected to the output terminal of the second step-up circuit and the second input terminal of the second step-up circuit is connected to the output terminal of the first step-up circuit. The voltage generating circuit may also include third and fourth step-up circuits and fifth and sixth step-up circuits having similar configurations.

Abstract: A semiconductor storage device according to the present embodiment includes a memory cell array including a plurality of memory cells. A plurality of word lines are electrically connected to control gates of the memory cells. A plurality of bit lines are electrically connected to one end of a current path of the memory cells. A sense amplifier part detects data stored in the selected memory cells. A power supply part converts an external power supply voltage to an internal power supply voltage and supplies the internal power supply voltage to the sense amplifier part. A power supply wire extends above the memory cell array and is provided to range from the power supply part to the sense amplifier part.

Abstract: A voltage generating circuit includes first and second step-up circuits, each having first and second input terminals and an output terminal and configured to increase a voltage level of an input signal supplied through the first input terminal and output the signal with the increased voltage level through the output terminal. The second input terminal of the first step-up circuit is connected to the output terminal of the second step-up circuit and the second input terminal of the second step-up circuit is connected to the output terminal of the first step-up circuit. The voltage generating circuit may also include third and fourth step-up circuits and fifth and sixth step-up circuits having similar configurations.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a first detecting circuit, a second detecting circuit, a switching circuit and a recovery control circuit. The first detecting circuit outputs a first detection signal which shows whether an externally supplied external power supply is equal to or more than a first voltage. The second detecting circuit outputs, at a higher speed than the first detecting circuit, a second detection signal which shows whether the external power supply is equal to or more than the first voltage. In a write operation, the switching circuit outputs the second detection signal output from the second detecting circuit. In an operation other than the write operation, the switching circuit outputs the first detection signal output from the first detecting circuit. The recovery control circuit terminates the write operation according to the second detection signal output from the switching circuit.

Abstract: A semiconductor storage device according to an embodiment includes multiple memory cells which electrically rewrite data, a well control circuit which outputs an erasure voltage to be applied to a well through an output terminal, a first pump circuit which outputs a voltage set by boosting an input voltage to the output terminal, a second pump circuit which outputs a voltage set by boosting the input voltage to the output terminal and outputs a voltage higher than an output voltage of the first pump circuit, a pump switching detecting circuit which outputs an assist signal to perform a boosting operation on at least one of the first pump circuit and the second pump circuit and an erase pulse control circuit which sets target voltages of the first pump circuit and the second pump circuit, on the basis of setting values to set a target voltage of the erasure voltage.

Abstract: A boosting circuit includes a clock control circuit which outputs a first reference clock signal by controlling the clock signal, and which outputs a second reference clock signal having a same period as that of the first reference clock signal, the second reference clock signal shifted in phase from the first reference clock signal. The boosting circuit includes a first pump clock generation circuit which outputs the first reference clock signal which is input thereto, as a first pump clock signal in accordance with a first pump flag signal. The boosting circuit includes a second pump clock generation circuit which outputs the second reference clock signal which is input thereto, as a second pump clock signal in accordance with a second pump flag signal. The boosting circuit includes a first charge pump which boosts an input voltage in accordance with the first pump clock signal. The boosting circuit includes a second charge pump which boosts an input voltage in accordance with the second pump clock signal.

Abstract: A boosting circuit includes first to fourth rectification elements, first to fourth MOS transistors, first to fourth capacitors, and a switch circuit. The switch circuit has a low level terminal connected to a first connection node between the first end of the third rectification element and the first end of the fourth rectification element, and a high level terminal connected to a second connection node between a second end of the third MOS transistor and a second end of the fourth MOS transistor. The switch circuit conducts changeover between a voltage at the low level terminal and a voltage at the high level terminal to output a resultant voltage to the output terminal.

Abstract: According to one embodiment, a current source circuit comprises a first circuit, a second circuit, and a current synthesizing circuit. The first circuit generates a first current having a positive temperature characteristic. The second circuit includes a feedback circuit configured to receive a first voltage having a negative temperature characteristic, and output a second voltage equal to the first voltage, and generates a second current having the negative temperature characteristic based on the second voltage. The current synthesizing circuit generates a constant current having an arbitrary temperature characteristic by adding the first and second currents.

Abstract: A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a first detecting circuit, a second detecting circuit, a switching circuit and a recovery control circuit. The first detecting circuit outputs a first detection signal which shows whether an externally supplied external power supply is equal to or more than a first voltage. The second detecting circuit outputs, at a higher speed than the first detecting circuit, a second detection signal which shows whether the external power supply is equal to or more than the first voltage. In a write operation, the switching circuit outputs the second detection signal output from the second detecting circuit. In an operation other than the write operation, the switching circuit outputs the first detection signal output from the first detecting circuit. The recovery control circuit terminates the write operation according to the second detection signal output from the switching circuit.

Abstract: A boosting circuit includes a clock control circuit which outputs a first reference clock signal by controlling the clock signal, and which outputs a second reference clock signal having a same period as that of the first reference clock signal, the second reference clock signal shifted in phase from the first reference clock signal. The boosting circuit includes a first pump clock generation circuit which outputs the first reference clock signal which is input thereto, as a first pump clock signal in accordance with a first pump flag signal. The boosting circuit includes a second pump clock generation circuit which outputs the second reference clock signal which is input thereto, as a second pump clock signal in accordance with a second pump flag signal. The boosting circuit includes a first charge pump which boosts an input voltage in accordance with the first pump clock signal. The boosting circuit includes a second charge pump which boosts an input voltage in accordance with the second pump clock signal.

Abstract: A semiconductor storage device according to an embodiment includes a plurality of memory cells which electrically rewrite data by controlling the amount of charges accumulated in a floating gate formed on a well through a tunnel insulating film. The semiconductor storage device includes a well control circuit which outputs an erasure voltage to be applied to the well through an output terminal. The semiconductor storage device includes a first pump circuit which outputs a voltage set by boosting an input voltage to the output terminal. The semiconductor storage device includes a second pump circuit which outputs a voltage set by boosting the input voltage to the output terminal and outputs a voltage higher than an output voltage of the first pump circuit. The semiconductor storage device includes a pump switching detecting circuit which outputs an assist signal to perform a boosting operation on at least one of the first pump circuit and the second pump circuit.

Abstract: A boosting circuit includes first to fourth rectification elements, first to fourth MOS transistors, first to fourth capacitors, and a switch circuit. The switch circuit has a low level terminal connected to a first connection node between the first end of the third rectification element and the first end of the fourth rectification element, and a high level terminal connected to a second connection node between a second end of the third MOS transistor and a second end of the fourth MOS transistor. The switch circuit conducts changeover between a voltage at the low level terminal and a voltage at the high level terminal to output a resultant voltage to the output terminal.

Abstract: A semiconductor memory device includes a boosting power supply circuit that boosts a first voltage to a second voltage, which is higher than an external power supply. A first bandgap reference (BGR) circuit operates on the second voltage generated by the boosting power supply circuit. Thereby, the power supply circuit generates a voltage by using a bandgap reference circuit.