Patents by Inventor Noriyuki Kawashima

Noriyuki Kawashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060273311
    Abstract: An organic semiconductor material is provided. The organic semiconductor material includes a polyacene derivative expressed by the following general formula (1): where each of R1 to R10 may be independently the same substituents or different substituents but all of R1, R4, R5, R6, R9 and R10 may never be hydrogen atoms at the same time, and where each of R1 to R10 is at least one kind of substituent selected from the group consisting of an aliphatic hydrocarbon group having a substituent and of which number of carbon atoms ranges of from 1 to 20, an aromatic hydrocarbon group having a substituent, a complex aromatic group having a substituent, a carboxyl group, a hydride, an ester group, a cyano group, a hydroxyl group, a halogen atom and a hydrogen atom. The organic semiconductor material can be dissolved into an organic solvent at low temperature (for example, room temperature) and is suitable for use with a coating process.
    Type: Application
    Filed: May 31, 2006
    Publication date: December 7, 2006
    Applicants: Sony Corporation, National University Corporation Hokkaido University
    Inventors: Takahiro Ohe, Noriyuki Kawashima, Tamotsu Takahashi, Ken-Ichiro Kanno
  • Publication number: 20060252205
    Abstract: There is provided a nonvolatile semiconductor storage device less subject to variances of electric characteristics among memory cells. A floating gate electrode provided on a substrate is made of two or more materials different in carrier trapping efficiency so as to accumulate carriers and thereby store data in the floating gate electrode. Thus a region without so large changes of the threshold voltage is produced, and the portion with a small change is used as the margin for circuit operations, thereby to eliminate variances among cells and realize high-speed operations.
    Type: Application
    Filed: July 6, 2006
    Publication date: November 9, 2006
    Inventors: Noriyuki Kawashima, Kenichi Taira
  • Patent number: 7098504
    Abstract: There is provided a nonvolatile semiconductor storage device less subject to variances of electric characteristics among memory cells. A floating gate electrode provided on a substrate is made of two or more materials different in carrier trapping efficiency so as to accumulate carriers and thereby store data in the floating gate electrode. Thus a region without so large changes of the threshold voltage is produced, and the portion with a small change is used as the margin for circuit operations, thereby to eliminate variances among cells and realize high-speed operations.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: August 29, 2006
    Assignee: Sony Corporation
    Inventors: Noriyuki Kawashima, Kenichi Taira
  • Publication number: 20030127680
    Abstract: Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in between. At the time of “the reading of data”, an electric potential is applied to the first control electrode. During “the reading of data”, a change in an electric potential between the conduction region and the storage region is prevented, and therefore, unintentional writing or erasing of information is prevented, so that written information can be accurately read out.
    Type: Application
    Filed: December 20, 2002
    Publication date: July 10, 2003
    Inventors: Kazumasa Nomoto, Noriyuki Kawashima, Ichiro Fujiwara, Kenichi Taira
  • Patent number: 6525379
    Abstract: Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in between. At the time of “the reading of data”, an electric potential is applied to the first control electrode. During “the reading of data”, a change in an electric potential between the conduction region and the storage region is prevented, and therefore, unintentional writing or erasing of information is prevented, so that written information can be accurately read out.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: February 25, 2003
    Assignee: Sony Corporation
    Inventors: Kazumasa Nomoto, Noriyuki Kawashima, Ichiro Fujiwara, Kenichi Taira
  • Publication number: 20020185674
    Abstract: There is provided a nonvolatile semiconductor storage device less subject to variances of electric characteristics among memory cells. A floating gate electrode provided on a substrate is made of two or more materials different in carrier trapping efficiency so as to accumulate carriers and thereby store data in the floating gate electrode. Thus a region without so large changes of the threshold voltage is produced, and the portion with a small change is used as the margin for circuit operations, thereby to eliminate variances among cells and realize high-speed operations.
    Type: Application
    Filed: June 5, 2002
    Publication date: December 12, 2002
    Inventors: Noriyuki Kawashima, Kenichi Taira
  • Publication number: 20020089012
    Abstract: Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in between. At the time of “the reading of data”, an electric potential is applied to the first control electrode. During “the reading of data”, a change in an electric potential between the conduction region and the storage region is prevented, and therefore, unintentional writing or erasing of information is prevented, so that written information can be accurately read out.
    Type: Application
    Filed: July 31, 2001
    Publication date: July 11, 2002
    Inventors: Kazumasa Nomoto, Noriyuki Kawashima, Ichiro Fujiwara, Kenichi Taira
  • Patent number: 6410412
    Abstract: Methods for fabricating memory devices having a multi-dot floating gate ensuring a desirable crystallization of a semiconductor film without ruining the flatness of the surface of the polycrystallized silicon layer and a tunnel oxide film, allowing desirable semiconductor dots to be produced, and allowing production of the memory devices having a multi-dot floating gate with ease and at low costs even when a substrate is made of glass or plastic.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: June 25, 2002
    Assignee: Sony Corporation
    Inventors: Kenichi Taira, Noriyuki Kawashima, Takashi Noguchi, Dharam Pal Gosain, Setsuo Usui
  • Patent number: 5418208
    Abstract: A laminated plastic card provided a lamination of a dye accepting layer, a substrate of paper or the like, and a back coat layer, on which lamination one or more patterns are printed with a volatile dye, and a transparent plastic film adhered on the lamination by an adhesive agent, wherein the adhesive agent is a saturated polyester resin having an average molecular weight of approximately 18,000 gm/mole and produced by condensation polymerization of polypropylene glycol or trimethylol propane and adipic acid or azelaic acid.
    Type: Grant
    Filed: May 6, 1993
    Date of Patent: May 23, 1995
    Assignee: Fujipla, Inc.
    Inventors: Hideyuki Takeda, Noriyuki Kawashima