Abstract: An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive type region, a first high concentration first conductive type region, and a second high concentration second conductive type region are formed in a surface of the second conductive type well. A third high concentration second conductive type region is formed in a surface of the first conductive type well. The first high concentration second conductive type region and the first high concentration first conductive type region are connected with a first power supply of a potential. The third high concentration second conductive type region is connected with a second power supply having a potential different from the potential of the first power supply.

Abstract: In a semiconductor device, a well region is formed in a semiconductor substrate, a transistor-formation region is defined in the well region. An electrostatic discharge protection device is produced in the transistor-formation region, and features a multi-finger structure including a plurality of fingers. A guard-ring is formed in the well region so as to surround the transistor-formation region, and a well blocking region is formed in the well region between the transistor-formation area and the guard-ring. A substrate resistance determination system is associated with the electrostatic discharge protection device to determine a substrate resistance distribution at the transistor-formation area such that snapbacks occur in all the fingers in a chain-reaction manner, and such that occurrence of a latch-up state is suppressed.

Abstract: An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive type region, a first high concentration first conductive type region, and a second high concentration second conductive type region are formed in a surface of the second conductive type well. A third high concentration second conductive type region is formed in a surface of the first conductive type well. The first high concentration second conductive type region and the first high concentration first conductive type region are connected with a first power supply of a potential. The third high concentration second conductive type region is connected with a second power supply having a potential different from the potential of the first power supply.

Abstract: An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive type region, a first high concentration first conductive type region, and a second high concentration second conductive type region are formed in a surface of the second conductive type well. A third high concentration second conductive type region is formed in a surface of the first conductive type well. The first high concentration second conductive type region and the first high concentration first conductive type region are connected with a first power supply of a potential. The third high concentration second conductive type region is connected with a second power supply having a potential different from the potential of the first power supply.

Abstract: In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.

Abstract: There is provided an electrostatic discharge protection device comprising a P conductive type first P well region 101 formed in a P type epitaxial layer 31 being deposited on a surface of a P+ substrate 30 having a prescribed thickness, an N conductive type first N well 101 a periphery thereof being brought into direct contact with and surrounded by a first P well region 101, P conductive type first P diffusion regions 121a and 121b, a P conductive type third P diffusion region 125, and an N conductive type second N diffusion region 223 arranged within a first P well region 101, and a P conductive type second P diffusion region 123 and an N conductive type first N diffusion region 221 arranged within a first N well 201.

Abstract: A multifinger ESD protection element has between an input wiring to which a surge current is input and a reference-potential wiring, 2n-number (where n is a natural number of 2 or greater) of fingers F1 to F2n. A drain resistor Rdi (i=1 to 2n), NMOS transistor Ti and source resistor Rsi are connected serially in each finger Fi in the order mentioned. A single unit Uj is constructed by two mutually adjacent fingers F2j?1 and F2j (where j is a natural number of 1 to n). In each unit the source of one transistor is connected to the gate of the other transistor and the source of this other transistor is connected to the gate of the first-mentioned transistor. The source S2j of finger F2j is connected to the source S2j+1 of the next unit Un+1. The 2n-number of fingers are connected in the form of a ring.

Abstract: Disclosed is a simulator in which there are provided a field plate for electrostatically charging a device under test, which comprises a first substrate (high resistance substrate) having a relatively high resistance and a substrate having a predetermined dielectric constant; and a ground plate for discharging the charged device which comprises a relatively high resistance member and further comprises an additional ground plate.

Abstract: In a semiconductor device, a well region is formed in a semiconductor substrate, a transistor-formation region is defined in the well region. An electrostatic discharge protection device is produced in the transistor-formation region, and features a multi-finger structure including a plurality of fingers. A guard-ring is formed in the well region so as to surround the transistor-formation region, and a well blocking region is formed in the well region between the transistor-formation area and the guard-ring.

Abstract: In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.

Abstract: A multifinger ESD protection element has between an input wiring to which a surge current is input and a reference-potential wiring, 2n-number (where n is a natural number of 2 or greater) of fingers F1 to F2n. A drain resistor Rdi (i=1 to 2n), NMOS transistor Ti and source resistor Rsi are connected serially in each finger Fi in the order mentioned. A single unit Uj is constructed by two mutually adjacent fingers F2j?1 and F2j (where j is a natural number of 1 to n). In each unit the source of one transistor is connected to the gate of the other transistor and the source of this other transistor is connected to the gate of the first-mentioned transistor. The source S2j of finger F2j is connected to the source S2j+1 of the next unit Un+1. The 2n-number of fingers are connected in the form of a ring.

Abstract: An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive type region, a first high concentration first conductive type region, and a second high concentration second conductive type region are formed in a surface of the second conductive type well. A third high concentration second conductive type region is formed in a surface of the first conductive type well. The first high concentration second conductive type region and the first high concentration first conductive type region are connected with a first power supply of a potential. The third high concentration second conductive type region is connected with a second power supply having a potential different from the potential of the first power supply.

Abstract: A coaxial probe includes a coaxial cable including an electrical conductor extending therethrough and projecting therefrom at an end thereof, a planar waveguide on which the electrical conductor projecting from the coaxial cable is mounted, and a sensor electrically connected to the electrical conductor through the planar waveguide. The planar waveguide may be comprised of a substrate, and a strip line formed on the substrate, the strip line being electrically connected at one end to the sensor and at the other end to the electrical conductor. The sensor may be comprised of a cantilever supported at a distal end thereof on the planar waveguide, and a probe mounted on a free end of the cantilever.

Abstract: An N well is formed in a surface of a P+ substrate and a P well is formed in such a way as to surround the N well. Then, a trigger tap (P+ diffusion region) is formed in the surface of the P well and two cathodes (N+ diffusion regions) are formed in such a way as to hold the trigger tap. Then, an anode (P+ diffusion region) is formed in the surface of the N well in a position facing the trigger tap and the cathode, and an N well pick-up diffusion (N+ diffusion region) is formed in such a way as to surround that side edge of the anode which does not face the cathode. Accordingly, the resistance between the end portion of the anode and the N well pick-up diffusion (N+ diffusion region) becomes lower than the resistance between the center portion of the anode and the N well pick-up diffusion.

Abstract: An N well is formed in a surface of a P+ substrate and a P well is formed in such a way as to surround the N well. Then, a trigger tap (P+ diffusion region) is formed in the surface of the P well and two cathodes (N+ diffusion regions) are formed in such a way as to hold the trigger tap. Then, an anode (P+ diffusion region) is formed in the surface of the N well in a position facing the trigger tap and the cathode, and an N well pick-up diffusion (N+ diffusion region) is formed in such a way as to surround that side edge of the anode which does not face the cathode. Accordingly, the resistance between the end portion of the anode and the N well pick-up diffusion (N+ diffusion region) becomes lower than the resistance between the center portion of the anode and the N well pick-up diffusion.

Abstract: There is provided an electrostatic discharge protection device comprising a P conductive type first P well region 101 formed in a P type epitaxial layer 31 being deposited on a surface of a P+ substrate 30 having a prescribed thickness, an N conductive type first N well 101 a periphery thereof being brought into direct contact with and surrounded by a first P well region 101, P conductive type first P diffusion regions 121a and 121b, a P conductive type third P diffusion region 125, and an N conductive type second N diffusion region 223 arranged within a first P well region 101, and a P conductive type second P diffusion region 123 and an N conductive type first N diffusion region 221 arranged within a first N well 201.

Abstract: A coaxial probe includes a coaxial cable including an electrical conductor extending therethrough and projecting therefrom at an end thereof, a planar waveguide on which the electrical conductor projecting from the coaxial cable is mounted, and a sensor electrically connected to the electrical conductor through the planar waveguide. The planar waveguide may be comprised of a substrate, and a strip line formed on the substrate, the strip line being electrically connected at one end to the sensor and at the other end to the electrical conductor. The sensor may be comprised of a cantilever supported at a distal end thereof on the planar waveguide, and a probe mounted on a free end of the cantilever.

Abstract: In an electrification quantity measurement apparatus including a probe for coming in contact with a measurement subject, a first resistor connected at a first terminal thereof to the probe, and a capacitor connected between a second terminal of the first resistor and ground, there is provided an offset current cancel means for canceling an offset current of the capacitor generated by an ionizer in order to measure an electrification quantity of the measurement subject placed in an ionizer environment.

Abstract: There is provided a semiconductor device including (a) a semiconductor substrate, (b) a gate insulating film formed on the semiconductor substrate, (c) a gate electrode formed on the gate insulating film, (d) L-shaped insulating films each comprising a first portion vertically extending on a sidewall of the gate electrode, and a second portion horizontally extending on the semiconductor substrate, and (e) raised source and drain layers formed on the semiconductor substrate in selected areas so that the raised source and drain layers make contact only with an end surface of the second portion. In the semiconductor device, since the insulating films are formed L-shaped, it is possible to reduce an area at which the insulating films make contact with the raised source and drain layers when the raised source and drain layers are formed by selective epitaxial growth. This prevents formation of facets, resulting in improving fabrication yield of a semiconductor device.

Abstract: A method of making a semiconductor device with a shallow (on the order of 50 nm) PN junction depth includes the steps of forming, on a region of a semiconductor substrate in which an impurity diffusion region having the shallow PN junction depth is to be formed, a selectively grown silicon layer (raised layer) containing a substance such as carbon which easily combines with point defects in the semiconductor substrate or a substance such as nitrogen which prevents an impurity providing an electrical conductivity from diffusing, ion-implanting an impurity of one conductivity type into the selectively grown silicon layer, and forming the diffusion region by activating the implanted impurity of one conductivity type and diffusing the impurity of one conductivity type into the semiconductor substrate, by means of heat treatment.