Abstract: An SRAM (Static Ransom Access Memory) has a refreshing unit for performing a refreshing operation to maintain a state of an electric charge in a memory cell in order to prevent stored data from being destructed by a latch-up phenomenon to maintain the stored data certainly even when a soft error occurs due to a neutron.

Abstract: The present method generates a greater number of hot holes than those generated by normal write/erase operations, thereby making it possible to evaluate an operation of a non-volatile memory with respect to hot holes. The present method performs a write operation to the non-volatile memory at lower temperatures than normal temperatures at normal use or/and at a lower operation voltage than a normal operation voltage at normal use, so as to generate a greater number of hot holes than those generated by normal write/erase operations between floating gates and drains of the memory, and then evaluates the operation of the memory while exposing it to the normal operation temperatures. This method is applicable to reliability tests of non-volatile memories such as FLASH memories.

Abstract: In a vehicle including a plurality of containing portions, namely, a front containing portion provided in an inner cover covering from the rear side a head pipe of a vehicle body frame at its front end and constituting a part of a vehicle body cover which can be locked in a fully closed condition, to facilitate the operation for releasing the lock conditions of the plurality of containing portions. A plurality of lock release operating buttons for respectively releasing the locked conditions of a plurality of containing portions inclusive of a front containing portion is disposed at an inner cover on a lateral side of the front containing portion.

Abstract: Includes the information search database as a knowledge database storing a plurality of causes, a plurality of questions having the cause-and-effect relation with the plurality of causes, and correlation levels showing a degree of the correlations between the causes and corresponding questions. The search control unit extracts certain questions out of the plurality of questions by the algorithm based on the correlation levels and extracting causes with high correlation levels out of the plurality of causes based on the searcher's answer result to each of the certain questions from the information database, and then presenting the causes thus extracted as the search result.

Abstract: A memory array is divided into a plurality of blocks. A plurality of mode storage units is so disposed as to correspond to the memory blocks. When a plurality of controllers outputs a mode setting instruction at the time of making of power, a setting unit 113 sets control information designated by the mode setting instruction to the corresponding mode storage unit. When different controllers gain access to a synchronous DRAM, an access operation is executed for the corresponding memory block in accordance with the control information.

Abstract: A multi-value memory that has an improved data maintain period has been disclosed and, in a multi-value nonvolatile semiconductor memory device comprising a multi-value memory cell having a floating-gate and able to store at least three values, the threshold values of the multi-value memory cell are set from a state in which the threshold values designate at least two boundary values that identify at least three values to a state in which a fixed quantity of charges are injected into the floating gate in a data write operation, the read data is determined from the relationship between the threshold values of the multi-value memory cell and the (at least) two boundary values, and increments (margins) A1, A2 and A3 in the threshold value from threshold values VT1, VT2 and VT3, which are the lower limits of ranges, due to the injection of charges into the floating gate in the data write operation are set so that the increment is larger for data corresponding to a state in which a larger quantity of charges are i

Abstract: A multi-value memory that has an improved data maintain period has been disclosed and, in a multi-value nonvolatile semiconductor memory device comprising a multi-value memory cell having a floating-gate and able to store at least three values, the threshold values of the multi-value memory cell are set from a state in which the threshold values designate at least two boundary values that identify at least three values to a state in which a fixed quantity of charges are injected into the floating gate in a data write operation, the read data is determined from the relationship between the threshold values of the multi-value memory cell and the (at least) two boundary values, and increments (margins) A1, A2 and A3 in the threshold value from threshold values VT1, VT2 and VT3, which are the lower limits of ranges, due to the injection of charges into the floating gate in the data write operation are set so that the increment is larger for data corresponding to a state in which a larger quantity of charges are i

Abstract: A multi-value memory that has an improved data maintain period has been disclosed and, in a multi-value nonvolatile semiconductor memory device comprising a multi-value memory cell having a floating gate and able to store at least three values, the threshold values of the multi-value memory cell are set from a state in which the threshold values designate at least two boundary values that identify at least three values to a state in which a fixed quantity of charges are injected into the floating gate in a data write operation, the read data is determined from the relationship between the threshold values of the multi-value memory cell and the (at least) two boundary values, and increments (margins) A1, A2 and A3 in the threshold value from threshold values VT1, VT2 and VT3, which are the lower limits of ranges, due to the injection of charges into the floating gate in the data write operation are set so that the increment is larger for data corresponding to a state in which a larger quantity of charges are i

Abstract: A memory testing method tests a memory by writing test data to and reading test data from the memory. Data is successively read from the memory is synchronism with a clock and the data is compared. The memory testing method then judges a defect in the memory based on a result of the comparison.

Abstract: Includes the information search database as a knowledge database storing a plurality of causes, a plurality of questions having the cause-and-effect relation with the plurality of causes, and correlation levels showing a degree of the correlations between the causes and corresponding questions. The search control unit extracts certain questions out of the plurality of questions by the algorithm based on the correlation levels and extracting causes with high correlation levels out of the plurality of causes based on the searcher's answer result to each of the certain questions from the information database, and then presenting the causes thus extracted as the search result.

Abstract: A memory testing method for testing a memory by writing test data to and reading test data from the memory, comprises the steps of (a) out of data successively read from the memory in synchronism with a clock, comparing one of two data consecutively read from the memory as an anticipated data with another of the two data, and judging a defect in the memory based on a result of a comparison made in the step (b).

Abstract: There is disclosed a structure of a magnetic memory device for writing/reading data to/from a magnetic memory cell including a plurality of magnetic layers. The magnetic memory device includes a plurality of magnetic memory cells, each magnetic memory cell being formed to have at least three magnetic layers. The plurality of magnetic memory cells are laid out along crossings between a plurality of first lines and a plurality of second lines that cross the first lines, respectively. The magnetic memory device selectively passes a current through the first lines and the second lines, and controls directions of magnetic moments of the first, second and third magnetic layers. Thus, the magnetic memory device writes data into a specific magnetic memory cell. In this structure, each of the first lines comprises at least two word lines.

Abstract: A memory array is divided into a plurality of blocks. A plurality of mode storage units is so disposed as to correspond to the memory blocks. When a plurality of controllers outputs a mode setting instruction at the time of making of power, a setting unit 113 sets control information designated by the mode setting instruction to the corresponding mode storage unit. When different controllers gain access to a synchronous DRAM, an access operation is executed for the corresponding memory block in accordance with the control information.

Abstract: There is disclosed a structure of a magnetic memory device for writing/reading data to/from a magnetic memory cell including a plurality of magnetic layers. The magnetic memory device includes a plurality of magnetic memory cells, each magnetic memory cell being formed to have at least three magnetic layers. The plurality of magnetic memory cells are laid out along crossings between a plurality of first lines and a plurality of second lines that cross the first lines, respectively. The magnetic memory device selectively passes a current through the first lines and the second lines, and controls directions of magnetic moments of the first, second and third magnetic layers. Thus, the magnetic memory device writes data into a specific magnetic memory cell. In this structure, each of the first lines comprises at least two word lines.

Abstract: A flash memory control apparatus and method which enables updating of data at high speed. The flash memory control apparatus includes a flash memory having a memory region which is divided into a plurality of sectors each including a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data; and a control device, coupled to the flash memory, for making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. The flash memory control method includes the steps of: (a) dividing a memory region of a flash memory into a plurality of sector; and (b) making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector.

Abstract: A flash memory control apparatus and method which enables updating of data at high speed. The flash memory control apparatus includes a flash memory having a memory region which is divided into a plurality of sectors each including a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data; and a control device, coupled to the flash memory, for making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. The flash memory control method includes the steps of: (a) dividing a memory region of a flash memory into a plurality of sector; and (b) making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector.

Abstract: A memory drive circuit includes at least one memory module constructed of a plurality of memory elements, a memory controller for driving said memory module, and a buffer, disposed between the memory module and the memory controller, for receiving a drive signal from the memory controller and transmitting the received drive signal to the memory module. Signal reflection noises produced in the memory module are absorbed by the buffer.

Abstract: A memory device having a memory element including a plurality of memory cells each designated by a row address signal and a column address signal, and a circuit for detecting a transition between the row address signal and the column address signal to thereby effect an equalize operation on the memory element. The supply of a row/column address signal including the row address signal and the column address signal to the memory element is cut off during a logical indeterminate period at the time of the transition. The row/column address signal immediately before its cutoff is held and the held signal is supplied to the memory element during the logical indeterminate period. Thus, a high-speed operation can be done by the equalize operation and the cutoff can provide the prevention of occurrence of a malfunction due to noise such as a glitch or the like.

Abstract: In a data management system for a programming-limited type semiconductor memory which is programmable a limited number of times and which includes a plurality of storage areas, a management unit manages, for each of the storage areas, the number of times that programming has been performed. A control unit selects one of the storage areas for which programming has been performed the smallest number of times and input data is written into the selected one of the storage areas, so that all the storage areas can be equally programmed.

Abstract: In an output circuit for driving a load connected to an output terminal in accordance with an input signal input to an input terminal, the output circuit connects to the input and output terminals, a first output buffer which operates when activated; connects in parallel to the first output buffer, a second output buffer which, when activated, operates with driving ability higher than the first output buffer; and activates the second output buffer for a predetermined period when the input signal is input and, after the period, activates the first output buffer.