Patents by Inventor Noriyuki Matsui

Noriyuki Matsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5481551
    Abstract: An IC element testing device includes a test pattern generating unit for generating test patterns, a power supply unit for generating a power supply voltage, a superposed voltage generating unit for generating a superposed voltage, and a superposing unit for superposing the superposed voltage on the power supply voltage and for outputting a superposed power supply voltage to an IC element to which the test patterns generated by the test pattern generating unit are applied.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: January 2, 1996
    Assignee: Fujitsu Limited
    Inventors: Rikizo Nakano, Noriyuki Matsui
  • Patent number: 5398348
    Abstract: A water urinal has a urinal body which includes a housing with an opening on its upper portion for receiving a valve used to supply flushing water to the urinal. The valve is attractively concealed within the body of the urinal and eliminates the necessity of embedding a valve in the wall surface on which the urinal is mounted. A cover, which covers and provides access to the valve receiving space within the urinal body, allows maintenance of the urinal without having to remove the urinal from the wall or break an opening in the wall.
    Type: Grant
    Filed: June 26, 1989
    Date of Patent: March 21, 1995
    Assignee: Toto Ltd.
    Inventors: Yukio Tashiro, Noriyuki Matsui, Ryuzo Fukuda, Manabu Hirahara, Naoki Tsukamura
  • Patent number: 5396466
    Abstract: A method of testing bit lines of a memory unit includes the steps of alternately writing a set of first binary values and a set of inverted first binary values to blocks having even block values and to blocks having odd block values for all storage elements within each of a plurality of blocks of the memory unit; setting the memory unit to a stressed condition; alternately reading pieces of binary data from first-row storage elements of the blocks having even block values and from final-row storage elements of the blocks having odd block values by repeatedly inverting a row value of a memory address and incrementing a block value of the memory address for each block; setting the memory unit to a normal condition; and repeating the first setting step, the alternate reading step, and the second setting step for all the columns of the plurality of the blocks.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: March 7, 1995
    Assignee: Fujitsu Limited
    Inventors: Rikizo Nakano, Noriyuki Matsui
  • Patent number: 5391922
    Abstract: A semiconductor element module is adapted to be mounted on a main body by insertion in a predetermined direction.
    Type: Grant
    Filed: June 24, 1994
    Date of Patent: February 21, 1995
    Assignee: Fujitsu Limited
    Inventor: Noriyuki Matsui