Abstract: A semiconductor device includes: a connection electrode formed on a side of a semiconductor element substrate opposed to a bump, where the semiconductor element substrate includes a semiconductor element; a passivation layer covering the semiconductor element substrate and an end portion of the connection electrode; and a barrier metal layer covering the connection electrode and a portion of the passivation layer so as to be electrically connected to the bump. A recess is formed in a portion of the passivation layer connected with the barrier metal layer.

Abstract: A semiconductor device includes: a semiconductor element (1) having an internal circuit (17); and electrode pads (22, 22, . . . ) provided for the semiconductor element (1). The electrode pads (22, 22, . . . ) are electrically connected to the internal circuit (17) via control portions (31) for controlling electrical connection between the electrode pads (22, 22, . . . ) and the internal circuit (17).

Abstract: A semiconductor device in which a chip 10 is mounted on a board, includes: a pad group A provided on the chip 10 and electrically connected to an internal circuit in the chip 10; and a test pad pattern B provided on a region of the chip 10 except for a region of the chip 10 where the pad group A is provided. The pad group A includes: pads 12a formed on a principal surface of the chip 10; bumps 16a respectively formed on the pads 12a with a barrier metal layer interposed therebetween, and electrically connected to the board. The test pad pattern B includes: test pads 12b formed on the principal surface of the chip 10; test bumps 16b respectively formed on the test pads 12b with a test barrier metal layer interposed therebetween, and interconnects 11b electrically connecting adjacent ones of the test pads 12b.

Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Abstract: A semiconductor element includes: a substrate having an integrated circuit; and a wire connection electrode and a bump connection electrode which are provided on a same main surface of the substrate as electrodes having a same connection function to the integrated circuit. The wire connection electrode is provided in a periphery of the main surface. The bump connection electrode is provided inside the wire connection electrode on the main surface. When a straight line dividing the main surface into two regions is determined, the wire connection electrode and the bump connection electrode are located opposite to each other with respect to the straight line.

Abstract: When manufacturing a semiconductor device by mounting a semiconductor chip 2 on a substrate 1 with a flip-chip method, projections 9 are formed between pads 4 arranged in multiple annular concentric layers on the semiconductor chip 2 other than pads 4 arranged along the innermost periphery thereof. On the substrate 1, bonding resin 3 is dispensed onto an area inside the innermost periphery along which the pads 4 are arranged. By heating and applying pressure, the bonding resin 3 is spread over the entire gap between the substrate 1 and the semiconductor chip 2 so as to secure the substrate 1 to the semiconductor chip 2 by the bonding resin 3, thereby preventing a void from being formed in an area outside the innermost periphery along which the pads 4 are arranged and thus stabilizing an electrical connection state between the semiconductor chip 2 and the substrate 1.

Abstract: The bump electrode 100 of the present invention has a structure in which dummy metals 111 are provided in the uppermost layer portion of a silicon 101 between a pad-form wiring metal 102 and a wiring metal 103 such that an edge of each dummy metal and an edge of the barrier metal 107 are not aligned in a line, and a lot of interfaces are formed between the dummy metals 111 and an interlayer film 140, and therefore expansion of a crack generated due to bump stress concentrated on the under-edge portion 109 below the barrier metal 107 between the pad-form wiring metal 102 and the wiring metal 103 is suppressed.

Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Abstract: A user PC 20 prepares a retrieve request by storing a SNMP command and a predetermined processing execution condition into a retrieve request of a SLP and transmits and outputs the prepared retrieve request to a printer 40 and others by multicast. Receiving the retrieve request, the printer 40 obtains and executes the SNMP command stored in the retrieve request of the SLP and processes a response to the retrieve request when the execution result meets the processing execution condition. Thus, the SNMP command is executed by receiving the retrieve request of the SLP and the response to the retrieve request of the SLP is processed corresponding to the execution result, it is not necessary to separately transmit or to obtain the request process of the SLP and the retrieve request of the SNMP through the network and the execution result of the SNMP command may be reflected to the process of the SLP.

Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Abstract: An optometric apparatus 2 according to the present invention comprises a body portion 5r provided with an optical system for a right eye for projecting a chart for the right eye in order to inspect visual function of both eye of an examinee and a body portion 5l provided with an optical system for a left eye for projecting a chart for the left eye, the optical systems for the right and left eyes projecting the same fusion patterns to perform fusion of the both eyes of the examinee.

Abstract: In an optometric apparatus of the present invention, optometric apparatus bodies 5l and 5r independently driven in right-and-left and up-and-down directions for optometry of an examinee 4, respectively, are provided on both sides of a face receiving device 6.

Abstract: In a semiconductor device having a multilayer interconnection structure, wires are formed by a damascene process, at least part of electrode pads includes a first conductive layer having a region provided for an electrical connection with an external unit. Herein, the first conductive layer is formed on a passivation film that is formed a semiconductor substrate and is indispensable for the multilayer interconnection structure.

Abstract: The technique of the present invention increases a variation in status used for management of print jobs, thereby enhancing utility of a printer. In a printing system constructed via a network LAN, a printer PRT includes a job management apparatus that manages statuses of print jobs in conformity with International Standard ISO/IEC10175-1. The job management apparatus has a create control module 6 in addition to diverse functional blocks for processing the print jobs based on the International Standard. When the user gives an instruction ‘create’ to a print job in a ‘held’ status, the create control module 6 creates a new daughter job from the print job in the ‘held’ status as a mother job and executes printing of either the mother job or the daughter job, while keeping at least one print job in the ‘held’ status. This arrangement enables a registered document to be reprinted iteratively at any arbitrary time.

Abstract: The technique of the present invention facilitates execution of proof printing, prior to main printing. In a printing system constructed via a network LAN, a printer PRT includes a job management apparatus that manages statuses of print jobs in conformity with International Standard ISO/IEC10175-1. The job management apparatus has a proofComplete control module 6 in addition to diverse functional blocks for processing the print jobs based on the International Standard. The proofComplete control module 6 functions to hold a print job with attribute information representing proof printing after conclusion of proof printing. Separate management of the print job with the proof printing attribute enables a single print job to be utilized for both proof printing and main printing. This arrangement effectively enhances the utility.

Abstract: In a semiconductor device, a pad metal has at least a portion located immediately under a probe region, and the portion is divided into a plurality of narrow metal layers each arranged in parallel with a traveling direction of a probe. Thus, it is possible to enhance surface flatness of the pad metal and to prevent a characteristic of a semiconductor device from deteriorating without complication in processing and increase in chip size.

Abstract: When an interlayer film (22) is formed to have a large thickness and an electrode pad (11) is partly or wholly led out from an active region (16), an I/O region (15) can be reduced in area. Thus, it is possible to reduce an area of a semiconductor device.

Abstract: The technique of the present invention facilitates execution of proof printing, prior to main printing. In a printing system constructed via a network LAN, a printer PRT includes a job management apparatus that manages statuses of print jobs in conformity with International Standard ISO/IEC10175-1. The job management apparatus has a proofComplete control module 6 in addition to diverse functional blocks for processing the print jobs based on the International Standard. The proofComplete control module 6 functions to hold a print job with attribute information representing proof printing after conclusion of proof printing. Separate management of the print job with the proof printing attribute enables a single print job to be utilized for both proof printing and main printing. This arrangement effectively enhances the utility.

Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.