Patents by Inventor Noriyuki Takahashi

Noriyuki Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110129325
    Abstract: The yield of semiconductor devices is to be enhanced. A tray is provided with a plurality of pockets each capable of accommodating a wafer level CSP, and each of the pockets is provided with a base for supporting a plurality of bumps of the wafer level CSP and side walls formed around the base. In the step-to-step carriage in the post-production process of the manufacture of wafer level CSPs and on like occasions, the base supports not the organic film but the plurality of solder bumps. For this reason, it is made possible to prevent the organic film from being flawed or coming off and adhering to the product as foreign matter, and as a result the quality and yield of the wafer level CSPs (semiconductor devices) can be improved.
    Type: Application
    Filed: February 4, 2011
    Publication date: June 2, 2011
    Inventor: Noriyuki TAKAHASHI
  • Patent number: 7923826
    Abstract: A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: April 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Noriyuki Takahashi, Mamoru Shishido
  • Patent number: 7915057
    Abstract: The yield of semiconductor devices is to be enhanced. A tray is provided with a plurality of pockets each capable of accommodating a wafer level CSP, and each of the pockets is provided with a base for supporting a plurality of bumps of the wafer level CSP and side walls formed around the base. In the step-to-step carriage in the post-production process of the manufacture of wafer level CSPs and on like occasions, the base supports not the organic film but the plurality of solder bumps. For this reason, it is made possible to prevent the organic film from being flawed or coming off and adhering to the product as foreign matter, and as a result the quality and yield of the wafer level CSPs (semiconductor devices) can be improved.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: March 29, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Noriyuki Takahashi
  • Publication number: 20110068450
    Abstract: A semiconductor device of a multi-pin structure using a lead frame is provided. The semiconductor device comprises a tab having a chip supporting surface, the chip supporting surface whose dimension is smaller than a back surface of a semiconductor chip, a plurality of leads arranged around the tab, the semiconductor chip mounted over the chip supporting surface of the tab, a plurality of suspending leads for supporting the tab, four bar leads arranged outside the tab so as to surround the tab and coupled to the suspending leads, a plurality of wires for coupling between the semiconductor chip and the leads, and a sealing body for sealing the semiconductor chip and the wires with resin, with first slits being formed respectively in first coupling portions of the bar leads for coupling with the suspending leads.
    Type: Application
    Filed: November 28, 2010
    Publication date: March 24, 2011
    Inventor: NORIYUKI TAKAHASHI
  • Publication number: 20110049709
    Abstract: Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping.
    Type: Application
    Filed: November 2, 2010
    Publication date: March 3, 2011
    Inventor: NORIYUKI TAKAHASHI
  • Publication number: 20110020984
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Application
    Filed: September 30, 2010
    Publication date: January 27, 2011
    Inventors: Tadashi MUNAKATA, Shingo OOSAKA, Mitsuru KINOSHITA, Yoshihiko YAMAGUCHI, Noriyuki TAKAHASHI
  • Patent number: 7847376
    Abstract: A semiconductor device of a multi-pin structure using a lead frame is provided. The semiconductor device comprises a tab having a chip supporting surface, the chip supporting surface whose dimension is smaller than a back surface of a semiconductor chip, a plurality of leads arranged around the tab, the semiconductor chip mounted over the chip supporting surface of the tab, a plurality of suspending leads for supporting the tab, four bar leads arranged outside the tab so as to surround the tab and coupled to the suspending leads, a plurality of wires for coupling between the semiconductor chip and the leads, and a sealing body for sealing the semiconductor chip and the wires with resin, with first slits being formed respectively in first coupling portions of the bar leads for coupling with the suspending leads.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: December 7, 2010
    Assignee: Renesas Electronics Corporation
    Inventor: Noriyuki Takahashi
  • Patent number: 7847388
    Abstract: Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: December 7, 2010
    Assignee: Renesas Electronics Corporation
    Inventor: Noriyuki Takahashi
  • Patent number: 7816185
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: October 19, 2010
    Assignees: Renesas Electronics Corporation, Renesas Northern Japan Semiconductor, Inc.
    Inventors: Tadashi Munakata, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamaguchi, Noriyuki Takahashi
  • Publication number: 20100248255
    Abstract: The present invention provides novel peptides with circulation-modulating activity. These peptides are useful as circulation-modulating agents and vasopressors because of their circulation-modulating activity, and can be used for treating diseases of the circulatory system such as myocardial infarction, ischemic heart disease, cerebral infarction, or the like.
    Type: Application
    Filed: July 28, 2006
    Publication date: September 30, 2010
    Applicants: KYOWA HAKKO KOGYO CO., LTD, JAPAN AS REPRESENTED BY THE PRESIDENT OF NATIONAL CARDIOVASCULAR CENTER, OSAKA UNIVERSITY
    Inventors: Motoo Yamasaki, Noriyuki Takahashi, Naoto Minamino, Kazuki Sasaki, Toshifumi Takao, Yoshinori Satomi
  • Publication number: 20100196219
    Abstract: In an exhaust emission control device, a selective reduction catalyst 5 having a property capable of selectively reacting NOx with ammonia even in the presence of oxygen is incorporated as NOx reduction catalyst in an exhaust pipe 4 and a particulate filter 13 is arranged upstream of the catalyst. Arranged in front of the particulate filter 13 is a burner 14 for injection of fuel in moderate quantity for ignition and combustion. Interposed between the particulate filter 13 and the selective reduction catalyst 5 is an oxidation catalyst 15 which conducts oxidation treatment of unburned HC in the exhaust gas 3 and urges oxidation reaction of NO in the exhaust gas 3 into NO2.
    Type: Application
    Filed: March 18, 2008
    Publication date: August 5, 2010
    Applicant: HINO MOTORS, LTD.
    Inventors: Hiroshi Endo, Noriyuki Takahashi
  • Publication number: 20100132333
    Abstract: The invention has its object to realize compact arrangement of particulate filter 5 and selective reduction catalyst 6 for improved mountability on a vehicle while a sufficient reaction time is ensured for generation of ammonia from urea water. In an exhaust emission control device with the filter 5 and the catalyst 6 capable of selectively reacting NOx with ammonia even in the presence of oxygen being incorporated in an exhaust pipe 4, urea water as reducing agent being addible therebetween, the filter 5 is arranged in a fore-and-aft direction of a vehicle and along a frame 10 of the vehicle. The catalyst 6 is arranged in a vicinity of an inlet end of the filter 5 and directed laterally outward of the vehicle. A communication passage 9 is arranged to guide the exhaust gas 3 discharged from an outlet end of the filter 5 to an inlet end of the catalyst 6 in a forwardly fold-back manner. A urea water adding injector 11 (urea water adding means) for addition of urea water is arranged midway of the passage 9.
    Type: Application
    Filed: March 13, 2008
    Publication date: June 3, 2010
    Applicant: HINO MOTORS, LTD.
    Inventors: Hiroshi Endo, Noriyuki Takahashi
  • Patent number: 7728412
    Abstract: A method of making a semiconductor device including a semiconductor chip having a plurality of pads, and a lead frame having a plurality of leads. Each of the plurality of leads has a mounting surface for mounting the semiconductor device, a wire connection surface having a thick portion, and a thin portion whose thickness is thinner than the thick portion. The length of each wire connection surface was furthermore formed shorter than the mounting surface, by arranging so that the thin portion of each lead dives below the semiconductor chip, securing the length of the mounting surface of each lead, a distance from the side face of the semiconductor chip to the side face of a molded body of the semiconductor device being shortened as much as possible, and the package size is brought close to chip size, with miniaturization of QFN.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: June 1, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Noriyuki Takahashi
  • Patent number: 7718008
    Abstract: The present invention provides a method for cleaning a photo mask without the need for removal of the pellicle mounted on the photo mask, without the large scale equipment for washing with a solution, with a small number of steps for cleaning and inspection, and without the increase of the production cost.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: May 18, 2010
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Shu Shimada, Noriyuki Takahashi, Hiroko Tanaka, Hiroyuki Ishii, Yusuke Shoji, Masashi Ohtsuki
  • Publication number: 20100075343
    Abstract: The present invention provides novel peptides with energy-modulating activity or circulatory function-modulating activity. The peptides of the present invention have energy-modulating activity or circulatory function-modulating activity and thus are useful for treating food consumption disorders and diseases of the circulatory system.
    Type: Application
    Filed: November 29, 2007
    Publication date: March 25, 2010
    Inventors: Motoo Yamasaki, Noriyuki Takahashi, Naoto Minamino, Kazuki Sasaki, Toshifumi Takao, Yoshinori Satomi, Yoichi Ueta
  • Publication number: 20090309213
    Abstract: A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.
    Type: Application
    Filed: June 9, 2009
    Publication date: December 17, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Noriyuki TAKAHASHI, Mamoru SHISHIDO
  • Publication number: 20090294965
    Abstract: Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping.
    Type: Application
    Filed: August 6, 2009
    Publication date: December 3, 2009
    Inventor: Noriyuki TAKAHASHI
  • Patent number: 7625779
    Abstract: Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: December 1, 2009
    Assignee: Renesas Technology Corp.
    Inventor: Noriyuki Takahashi
  • Publication number: 20090291529
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Application
    Filed: August 3, 2009
    Publication date: November 26, 2009
    Inventors: TADASHI MUNAKATA, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamaguchi, Noriyuki Takahashi
  • Patent number: 7615872
    Abstract: A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: November 10, 2009
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Noriyuki Takahashi, Masahiro Ichitani, Rumiko Ichitani, legal representative, Kazuhiro Ichitani, legal representative, Sachiyo Ichitani, legal representative