Abstract: Methods, machine readable media and systems for near-field electromagnetic simulation for side-channel emission analysis of an integrated circuit (IC) are described. In one embodiment, a method can include the following operations: simulating EM field strengths for a plurality of grid partitions of a circuit area of the IC based on a cryptographic work load applied to a model of the IC; identifying one or more of the grid partitions as a security sensitive region for the IC based on the EM field strengths, wherein one or more grid partitions outside of the security sensitive region are identified as non-security sensitive regions for the IC; and simulating EM fields for the IC to perform the EM side-channel emission analysis, wherein contributions of the EM fields from the non-security sensitive regions for the EM side-channel emission analysis are based on a linear superposition of wire currents in the non-security sensitive regions of the IC.

Abstract: A method in one embodiment creates a model of an authentic IC for use in comparisons with counterfeit ICs. The model can be created by determining a first or initial set of points of interest (POIs) on the simulated physical (e.g., gate level) layout and simulating side channel leakage from each POI and then expanding the size of the POI and repeating the simulation and comparing successive simulation results (between successive sizes of POIs for a given POI) to determine if a solution for the size of the POI has converged. The final POIs are then processed in a simulation that can use multiple payloads (e.g., cryptographic data) over the entire set of final POIs, and the resulting data set can be used to create the model.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. The methods can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC); performing a thermal simulation for each respective template of the IC based on a sequence of power patterns of tiles of the respective template; and training a neural network with a plurality of training data collected via thermal simulations performed for the templates of the IC. These systems and methods can use a machine learning predictor, that has been trained to determine a transient temperature rise across an entire IC, and then append the determined transient temperature rise to a system level thermal profile of the IC.

Abstract: A method in one embodiment creates a model of an authentic IC for use in comparisons with counterfeit ICs. The model can be created by determining a first or initial set of points of interest (POIs) on the simulated physical (e.g., gate level) layout and simulating side channel leakage from each POI and then expanding the size of the POI and repeating the simulation and comparing successive simulation results (between successive sizes of POIs for a given POI) to determine if a solution for the size of the POI has converged. The final POIs are then processed in a simulation that can use multiple payloads (e.g., cryptographic data) over the entire set of final POIs, and the resulting data set can be used to create the model.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.

Abstract: Techniques for security vulnerability assessment of security-sensitive circuit designs are described. A placement of security-sensitive components of a design may be based on constraints related to how far apart a relevant set of security-sensitive components are allowed without consuming too much power and how to optimize the placement to minimize electromagnetic side-channel leakage or other security vulnerabilities. In one embodiment, a method may receive data that includes a representation of a design of an IC and may identify security-sensitive components of the design from the data. The method may determine a placement for the design based on constraints on a level of security vulnerabilities of the security-sensitive components and may perform a power simulation for the design based on the placement. The method may generate an assessment of the level of security vulnerabilities of the security-sensitive components based on the power simulation to adjust the placement for the design.

Abstract: A specification for a semi-conductor chip is received. The specification specifies a set of photomasks associated with a metal layer of the semi-conductor chip. Multiple portions of an area of the metal layer are identified. A respective image is generated for each portion of the area based on the photomasks. A respective drawn density of metal wires for each portion of the area is calculated. A trained machine learning model is invoked to predict a respective silicon density of metal wires for each respective portion of the area based on an image and a drawn density for the respective portion of the area. A silicon density for the area of the metal layer is calculated based on a combination of predicted silicon densities for the multiple portions of the area. The combination is based on an average value of the predicted silicon densities for the multiple portions of the area.

Abstract: Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method can determine, from a gate level representation of a circuit in a layout on a die of an IC, a first set of paths through the circuit that process security related data during operation of the circuit, the circuit including a second set of paths that do not process security related data; and the method can further determine, in a simulation of power consumption in the first set of paths but not the second set of paths, power consumption values in the first set of paths to determine potential security leakage of the security related data in the circuit. The method can further determine, from the power consumption values, positions in the layout for inserting virtual probes on the die for use in measuring security metrics that indicate potential leakage of the security related data. The insertion of the virtual probes is relative to the actual simulated layout of the die.

Abstract: Methods, machine readable media and systems for performing side channel analysis are described. In one embodiment, a method, performed on a data processing system, can receive input data that contains an RTL representation of a design of a circuit and then determine, from the input data, a set of registers that store security related data during operation of the circuit, wherein the set of registers are a subset of all of the registers in the design. The method then determines, in a simulation of power consumption of the set of registers in the RTL representation, security metrics that indicate a level of potential leakage of security related data such as secret or private cryptographic keys.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.

Abstract: Methods, machine readable media and systems for simulating the leakage of sensitive data in an integrated circuit, such as cryptographic data or keys, are described. In one embodiment, a method can include the following operations: performing a first dynamic voltage drop (DVD) simulation on a plurality of locations, distributed across an integrated circuit (IC), based on a physical model that specifies physical layout of components on the IC, the IC storing sensitive data in locations of the layout; performing an IC level side channel correlation analysis between each of the locations and the sensitive data based on the results of the first DVD simulation; and selecting, based upon the IC level side channel correlation analysis, a subset of the locations for further simulations to simulate leakage of the sensitive data. Other methods, media and systems are disclosed.

Abstract: Circuit design techniques can use a trained predictor to predict key dynamic current metrics (such as peak current, peak time, pulse width and total charge) for a gate in a circuit library, where the predictor has been trained over different combinations of different input transition slews and different output fanout models. A dynamic current model solver can be used for a gate in the cell library to derive waveforms (of current versus time) for the different combinations, and a predictor, such as a neural network, can be trained with the outputs from the solver for the different combinations. The trained predictor can be used in a runtime simulation to solve for the dynamic current demand model of the various gates in a circuit design (such as all of the gates in an integrated circuit). In one embodiment, adaptive clustering of the various instances of a gate may be used to reduce a plurality of such gates in a cluster to a representative gate that acts as a centroid instance of the gate in the cluster.

Abstract: Methods, machine readable media and systems for near-field electromagnetic simulation for side-channel emission analysis of an integrated circuit (IC) are described. In one embodiment, a method can include the following operations: simulating EM field strengths for a plurality of grid partitions of a circuit area of the IC based on a cryptographic work load applied to a model of the IC; identifying one or more of the grid partitions as a security sensitive region for the IC based on the EM field strengths, wherein one or more grid partitions outside of the security sensitive region are identified as non-security sensitive regions for the IC; and simulating EM fields for the IC to perform the EM side-channel emission analysis, wherein contributions of the EM fields from the non-security sensitive regions for the EM side-channel emission analysis are based on a linear superposition of wire currents in the non-security sensitive regions of the IC.

Abstract: Example systems and methods are disclosed for performing a timing analysis on a circuit design. A plurality of switching scenarios are identified for the circuit design. One or more predictive models are applied to predict a subset of the plurality of switching scenarios that are likely to cause timing paths with critical timing problems. A dynamic voltage analysis is performed on timing paths based on the subset of switching scenarios. The one or more predictive models are applied to predict a set of critical timing paths based on the subset of switching scenarios that are likely to cause critical timing problems, the one or more predictive models taking into account the dynamic voltage analysis. A timing analysis is the performed on the set of critical timing paths.

Abstract: Methods, machine readable media and systems for simulating the leakage of sensitive data in an integrated circuit, such as cryptographic data or keys, are described. In one embodiment, a method can include the following operations: performing a first dynamic voltage drop (DVD) simulation on a plurality of locations, distributed across an integrated circuit (IC), based on a physical model that specifies physical layout of components on the IC, the IC storing sensitive data in locations of the layout; performing an IC level side channel correlation analysis between each of the locations and the sensitive data based on the results of the first DVD simulation; and selecting, based upon the IC level side channel correlation analysis, a subset of the locations for further simulations to simulate leakage of the sensitive data. Other methods, media and systems are disclosed.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. The methods can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC); performing a thermal simulation for each respective template of the IC based on a sequence of power patterns of tiles of the respective template; and training a neural network with a plurality of training data collected via thermal simulations performed for the templates of the IC. These systems and methods can use a machine learning predictor, that has been trained to determine a transient temperature rise across an entire IC, and then append the determined transient temperature rise to a system level thermal profile of the IC.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.

Abstract: Data is received that characterizes a chip in the package system (CPS) having a plurality of wires and vias. Thereafter, using the received data, a chip power calculation is performed. The chip power calculated is used to generate a thermal-aware power map. Further, package and system level thermal analysis is performed using the power map to generate a tile-based CPS thermal profile. A plurality of chip finite element sub-models are then generated that each correspond to a different tile. A thermal field solution is solved for each sub-model so that, for each wire, wire temperature rises are extracted from the corresponding the chip sub-model analysis and combined with temperature values from the CPS thermal profile. This extracting and combining is then used to generate a back-annotation file covering each metal wire and via in the CPS.