Abstract: Computer-implemented systems and methods are provided for modeling a charge pump. A relationship between an output voltage of the charge pump and a loading condition is determined. A frequency-domain analysis is performed at multiple frequencies to determine an impedance function representative of the charge pump's impedance at each of the multiple frequencies. A vector-fitting algorithm is applied to approximate the impedance function using a plurality of poles and residues. A circuit is synthesized based on the plurality of poles and residues. A model for the charge pump is generated, where the model includes the synthesized circuit and components that model the relationship between the output voltage and the loading condition.

Abstract: Machine assisted systems and methods for detecting unreliable circuit patterns are described. These systems and methods can use a machine learning classifier, that has been trained to recognize such circuit patterns, to detect the unreliable circuit patterns without requiring computationally expensive simulations of a circuit netlist which can be over a million devices (e.g. over a million FETs). The classifier, once trained, can recognize unreliable circuit patterns quickly and can be updated over time as new unreliable circuit patterns are discovered from simulations or other sources.

Abstract: Data is received that characterizes a chip in the package system (CPS) having a plurality of wires and vias. Thereafter, using the received data, a chip power calculation is performed. The chip power calculated is used to generate a thermal-aware power map. Further, package and system level thermal analysis is performed using the power map to generate a tile-based CPS thermal profile. A plurality of chip finite element sub-models are then generated that each correspond to a different tile. A thermal field solution is solved for each sub-model so that, for each wire, wire temperature rises are extracted from the corresponding the chip sub-model analysis and combined with temperature values from the CPS thermal profile. This extracting and combining is then used to generate a back-annotation file covering each metal wire and via in the CPS.

Abstract: Computer-implemented systems and methods for modeling low-dropout (LDO) regulators and charge pumps are provided. A relationship between an output voltage of an LDO regulator or charge pump and a loading condition is determined. A frequency-domain analysis is performed at multiple frequencies to determine an impedance function representative of an impedance of the LDO regulator or charge pump at each of the multiple frequencies. A vector-fitting algorithm is applied to approximate the impedance function using a plurality of poles and residues. A circuit is synthesized based on the plurality of poles and residues. A model for the LDO regulator or charge pump is generated, where the model includes the synthesized circuit and components that model the relationship between the output voltage and the loading condition.

Abstract: Systems and methods are provided for reducing processing time of an automated engineering design. A repository of engineering design rule violations and corresponding waiver decisions regarding the design rule violations is accessed. A clustering operation is performed on violations in the repository to form clusters of violations based on one or more characteristics of the violations. Waiver decisions associated with violations in each cluster are evaluated to assign a risk level to each cluster. A plurality of detected engineering design rule violations associated with an engineering design are identified. Each of the detected violations is iterated through to determine which cluster that detected violation belongs. Detected violations associated with low risk clusters are automatically to approve the engineering design.

Abstract: Data is received that characterizes a chip in the package system (CPS) having a plurality of wires and vias. Thereafter, using the received data, a chip power calculation is performed. The chip power calculated is used to generate a thermal-aware power map. Further, package and system level thermal analysis is performed using the power map to generate a tile-based CPS thermal profile. A plurality of chip finite element sub-models are then generated that each correspond to a different tile. A thermal field solution is solved for each sub-model so that, for each wire, wire temperature rises are extracted from the corresponding the chip sub-model analysis and combined with temperature values from the CPS thermal profile. This extracting and combining is then used to generate a back-annotation file covering each metal wire and via in the CPS.

Abstract: Systems and methods are provided for estimating a temperature of a wire of an integrated circuit (IC) chip having a plurality of heat-generating components. For each of the heat-generating components, a temperature of the heat-generating component is computed. For each of the heat-generating components, a decay profile defining a thermal coupling from the heat-generating component to wires of the IC chip is computed. For each of the heat-generating components, a temperature elevation on the wire caused by the heat-generating component is computed. The temperature elevation is computed based on the temperature and decay profile of the heat-generating component and a spatial relationship between the wire and the heat-generating component. A total temperature elevation on the wire is computed by summing the temperature elevation of each of the heat-generating components. The heat-generating components include a plurality of wires of the IC chip and at least one device of the IC chip.

Abstract: A system and method to reduce leakage power consumption of electronic devices. In addition to assigning threshold voltages, sizes of the transistors within the device may be varied to provide a range of options to meet the timing requirements while minimizing the leakage power consumption.

Abstract: An efficient inductance modeling approach for on-chip power-ground wires using their effective self-loop-inductances is disclosed. Instead of extracting the inductive coupling between every two parallel wires and putting this huge number inductance elements into circuit simulation, this technique determines the effective self-loop-inductance for each power or ground wire segment and only generates a circuit with these effective self-inductors for simulation. This approach greatly reduces the circuit size and makes the full-chip power-ground simulation with the consideration of inductance feasible.

Abstract: A method determines a plurality of clock delay values. Each delay value is associated with a delay element on a clock line leading to a clock sink in a synchronous circuit. The method determines an initial set of delay values and executes an optimization algorithm, beginning with the initial set of delay values, to arrive at a set of delay values that at least approximately meets an criteria while satisfying timing constraints associated with selected pairs of logically connected clock sinks. In a preferred form, the optimization algorithm is a genetic algorithm or a gradient descent algorithm. The genetic algorithm involves selecting parent sets of delay values, crossing over so as to produce a child set of delay values, mutating the child set of delay values, evaluating how well the child set of delay values meets the criteria, and conditionally discarding the child set on the basis of the evaluating step.

Abstract: A method reduces noise resulting from a current surge in a circuit. A plurality of loading elements, parallel with the circuit being protected, are connected sequentially and disconnected. The connection of the loading elements results in a ramping up of current through the circuit without a sudden surge. In a preferred embodiment, an apparatus for slowing a current change in a circuit is described. The apparatus comprises a plurality of loading elements placed in parallel with the circuit, each of the elements providing a path for current flow, and a control circuit for selectively opening or closing at least one of said paths to prevent or enable current flow through the at least one of the paths.

Abstract: Methods for efficient integrated circuit (“IC”) dynamic IR-drop analysis algorithm are disclosed. In one aspect, the disclosed methods eliminate the need for peak-power input stimulus vectors or Verilog's value change dump (“VCD”). Rather than performing transient simulation over a long set of input vectors to determine the worst dynamic IR, the disclosed method statistically determines the switching direction and the timing for each instance based on its block or module switching scenario. Full-chip transient simulation, including the RLC extracted from the power-ground network, is then performed accordingly over a few clock cycles. This approach makes feasible full-chip dynamic IR-drop verification with the consideration of power-ground inductance and capacitance. Furthermore, methods are disclosed for optimal decoupling-capacitor insertion for remedying power-integrity problems, including their amounts and locations.

Abstract: A method for efficient integrated circuit (“IC”) dynamic IR-drop analysis algorithm is disclosed. In one aspect, this method eliminates the need for peak-power input stimulus vectors or Verilog's value change dump (“VCD”). Rather than performing transient simulation over a long set of input vectors to determine the worst dynamic IR-drop, the disclosed method statistically determines the switching direction and the timing for each instance based on its block or module switching scenario. Full-chip transient simulation, including the RLC extracted from the power-ground network, is then performed accordingly over a few clock cycles. This approach makes feasible full-chip dynamic IR verification with the consideration of power-ground inductance and capacitance.

Abstract: A logic gate circuit and related methods and apparatus exhibit reduced voltage swing and thereby consume less power. The circuit is connected to a plurality of input signals and a clock signal. The circuit produces an output. The circuit comprises a node, a pull-down network and an N-type MOS transistor. The pull-down network is connected to the node, a first reference voltage, the plurality of inputs and the clock signal. The N-type MOS transistor is connected between the node and a second reference voltage. The N-type MOS transistor is also connected to a complement of the clock signal. A method of the invention accepts a complement of a clock signal and pre-charges a node to a voltage less than a power supply voltage, in response to the complement of the clock signal. The method also accepts a plurality of input signals and accepts the clock signal. The method conditionally discharges the node, in response to the clock signal, on the basis of the plurality of input signals.

Abstract: A system and method to reduce leakage power consumption of electronic devices. In addition to assigning threshold voltages, sizes of the transistors within the device may be varied to provide a range of options to meet the timing requirements while minimizing the leakage power consumption.

Abstract: A method reduces noise resulting from a current surge in a circuit. A plurality of loading elements, parallel with the circuit being protected, are connected sequentially and disconnected. The connection of the loading elements results in a ramping up of current through the circuit without a sudden surge. In a preferred embodiment, an apparatus for slowing a current change in a circuit is described. The apparatus comprises a plurality of loading elements placed in parallel with the circuit, each of the elements providing a path for current flow, and a control circuit for selectively opening or closing at least one of said paths to prevent or enable current flow through the at least one of the paths.

Abstract: An RLC module is configured to provide a simplified circuit modeling of a selected circuit net (or portion) of an electronic circuit. The RLC module may be configured to substitute an RLC circuit model for the selected circuit net, where the effective values of the capacitance and inductance for the RLC circuit model are retrieved from a table of capacitance and inductance values. A set of interconnect geometry factors (e.g., line length, line width, driver/receiver length, etc.) that describes the circuit net is used as an index into the table of capacitance and inductance values. The retrieved values of the effective capacitance and inductances values may be used to calculate a delay for the RLC circuit model. The RLC module may provide the capability to quickly calculate a delay for a selected circuit net without using computationally intensive calculations for inductance and capacitance values of circuit nets.

Abstract: A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.

Abstract: Power surges in electrical systems, such as microprocessors, may be reduced by gradually applying power to resources, such as the floating point unit, to an active state. Also, performance penalty may be minimized by predicting ahead of time when a resource will be needed. In this manner, the power to the resource may be gradually applied so that the resource is active when it is actually needed. Modules may be included that predicts when a resource is needed based on instructions prefetched instruction from a pipeline of a microprocessor. Based on the prediction, power control modules may control the power to the necessary resource gradually.

Abstract: An RLC module is configured to provide a simplified circuit modeling of a selected circuit net (or portion) of an electronic circuit. The RLC module may be configured to substitute an RLC circuit model for the selected circuit net, where the effective values of the capacitance and inductance for the RLC circuit model are retrieved from a table of capacitance and inductance values. A set of interconnect geometry factors (e.g., line length, line width, driver/receiver length, etc.) that describes the circuit net is used as an index into the table of capacitance and inductance values. The retrieved values of the effective capacitance and inductances values may be used to calculate a delay for the RLC circuit model. The RLC module may provide the capability to quickly calculate a delay for a selected circuit net without using computationally intensive calculations for inductance and capacitance values of circuit nets.