Patents by Inventor Norman Day

Norman Day has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7530068
    Abstract: A method and apparatus are provided for efficiently managing limited resources is a given computer system. The system utilizes a token manager that assigns tokens to groups of associated requestors. The tokens are then utilized by the requesters to occupy the given resource. The allocation of these tokens, thus, prevents such problems as denial of service due to a lack of available resources.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: May 5, 2009
    Assignee: International Business Machines Corporation
    Inventors: Scott Douglas Clark, Michael Norman Day, Charles Ray Johns, Andrew Henry Wottreng
  • Patent number: 7523157
    Abstract: Managing a computer system's multiple processors as devices. The operating system accesses the multiple processors using processor device modules loaded into the operating system to facilitate a communication between an application requesting access to a processor and the processor. A device-like access is determined for accessing each one of the processors similar to device-like access for other devices in the system such as disk drives, printers, etc. An application seeking access to a processor issues device-oriented instructions for processing data, and in addition, the application provides the processor with the data to be processed. The processor processes the data according to the instructions provided by the application.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: April 21, 2009
    Assignee: International Business Machines Corporation
    Inventors: Maximino Aguilar, Jr., Michael Norman Day, Mark Richard Nutter, James Michael Stafford
  • Patent number: 7516456
    Abstract: A method for an asymmetric heterogeneous multi-threaded operating system is presented. A processing unit (PU) provides a trusted mode environment in which an operating system executes. A heterogeneous processor environment includes a synergistic processing unit (SPU) that does not provide trusted mode capabilities. The PU operating system uses two separate and distinct schedulers which are a PU scheduler and an SPU scheduler to schedule tasks on a PU and an SPU, respectively. In one embodiment, the heterogeneous processor environment includes a plurality of SPUs. In this embodiment, the SPU scheduler may use a single SPU run queue to schedule tasks for the plurality of SPUs or, the SPU scheduler may use a plurality of run queues to schedule SPU tasks whereby each of the run queues correspond to a particular SPU.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: April 7, 2009
    Assignee: International Business Machines Corporation
    Inventors: Maximino Aguilar, Jr., Michael Norman Day, Mark Richard Nutter, James Michael Stafford
  • Patent number: 7496917
    Abstract: A method is provided to allow virtual devices that use a plurality of processors in a multiprocessor systems, such as the BE environment. Using this method, a synergistic processing unit (SPU) can either be dedicated to performing a particular function (i.e., audio, video, etc.) or a single SPU can be programmed to perform several functions on behalf of the other processors in the system. The application, preferably running in one of the primary (PU) processors, issues IOCTL commands through device drivers that correspond to SPUs. The kernel managing the primary processors responds by sending an appropriate message to the SPU that is performing the dedicated function. Using this method, an SPU can be virtualized for swapping multiple tasks or dedicated to performing a particular task.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: February 24, 2009
    Assignee: International Business Machines Corporation
    Inventors: Daniel Alan Brokenshire, Michael Norman Day, Barry L Minor, Mark Richard Nutter
  • Patent number: 7478390
    Abstract: A task queue manager manages the task queues corresponding to virtual devices. When a virtual device function is requested, the task queue manager determines whether an SPU is currently assigned to the virtual device task. If an SPU is already assigned, the request is queued in a task queue being read by the SPU. If an SPU has not been assigned, the task queue manager assigns one of the SPUs to the task queue. The queue manager assigns the task based upon which SPU is least busy as well as whether one of the SPUs recently performed the virtual device function. If an SPU recently performed the virtual device function, it is more likely that the code used to perform the function is still in the SPU's local memory and will not have to be retrieved from shared common memory using DMA operations.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: January 13, 2009
    Assignee: International Business Machines Corporation
    Inventors: Daniel Alan Brokenshire, Michael Norman Day, Barry L Minor, Mark Richard Nutter, VanDung Dang To
  • Patent number: 7475257
    Abstract: A system and method are provided to dedicate one or more processors in a multiprocessing system to performing encryption functions. When the system initializes, one of the synergistic processing unit (SPU) processors is configured to run in a secure mode wherein the local memory included with the dedicated SPU is not shared with the other processors. One or more encryption keys are stored in the local memory during initialization. During initialization, the SPUs receive nonvolatile data, such as the encryption keys, from nonvolatile register space. This information is made available to the SPU during initialization before the SPUs local storage might be mapped to a common memory map. In one embodiment, the mapping is performed by another processing unit (PU) that maps the shared SPUs' local storage to a common memory map.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: January 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Maximino Aguilar, Jr., David Craft, Michael Norman Day, Akiyuki Hatakeyama, Harm Peter Hofstee, Masakazu Suzuoki
  • Publication number: 20080301695
    Abstract: A computer system's multiple processors are managed as devices. The operating system accesses the multiple processors using processor device modules loaded into the operating system to facilitate a communication between an application requesting access to a processor and the processor. A device-like access is determined for accessing each one of the processors similar to device-like access for other devices in the system such as disk drives, printers, etc. An application seeking access to a processor issues device-oriented instructions for processing data, and in addition, the application provides the processor with the data to be processed. The processor processes the data according to the instructions provided by the application.
    Type: Application
    Filed: July 19, 2008
    Publication date: December 4, 2008
    Applicant: International Business Machines Corporation
    Inventors: Maximino Aguilar, JR., Michael Norman Day, Mark Richard Nutter, James Michael Stafford
  • Publication number: 20080282064
    Abstract: A system and method for speculative assistance to a thread in a heterogeneous processing environment is provided. A first set of instructions is identified in a source code representation (e.g., a source code file) that is suitable for speculative execution. The identified set of instructions are analyzed to determine the processing requirements. Based on the analysis, a processor type is identified that will be used to execute the identified first set of instructions based. The processor type is selected from more than one processor types that are included in the heterogeneous processing environment. The heterogeneous processing environment includes more than one heterogeneous processing cores in a single silicon substrate. The various processing cores can utilize different instruction set architectures (ISAs). An object code representation is then generated for the identified first set of instructions with the object code representation being adapted to execute on the determined type of processor.
    Type: Application
    Filed: May 7, 2007
    Publication date: November 13, 2008
    Inventors: Michael Norman Day, Michael Karl Gschwind, John Kevin Patrick O'Brien, Kathryn O'Brien
  • Publication number: 20080263091
    Abstract: Asynchronously traversing a disjoint linked data structure is presented. A synergistic processing unit (SPU) includes a handler that works in conjunction with a memory flow controller (MFC) to traverse a disjoint linked data structure. The handler compares a search value with a node value, and provides the MFC with an effective address of the next node to traverse based upon the comparison. In turn, the MFC retrieves the corresponding node data from system memory and stores the node data in the SPU's local storage area. The MFC stalls processing and sends an asynchronous event interrupt to the SPU which, as a result, instructs the handler to retrieve and compare the latest node data in the local storage area with the search value. The traversal continues until the handler matches the search value with a node value or until the handler determines a failed search.
    Type: Application
    Filed: June 27, 2008
    Publication date: October 23, 2008
    Applicant: International Business Machines Corporation
    Inventors: Maximino Aguilar, Michael Norman Day, Mark Richard Nutter
  • Publication number: 20080235679
    Abstract: Loading software on a plurality of processors is presented. A processing unit (PU) retrieves a file from system memory and loads it into its internal memory. The PU extracts a processor type from the file's header which identifies whether the file should execute on the PU or a synergistic processing unit (SPU). If an SPU should execute the file, the PU DMA's the file to the SPU for execution. In one embodiment, the file is a combined file which includes both PU and SPU code. In this embodiment, the PU identifies one or more section headers included in the file which indicates embedded SPU code within the combined file. In this embodiment, the PU extracts the SPU code from the combined file and DMA's the extracted code to an SPU for execution.
    Type: Application
    Filed: June 2, 2008
    Publication date: September 25, 2008
    Applicant: International Business Machines Corporation
    Inventors: Maximino Aguilar, Alex Chunghen Chow, Michael Norman Day, Michael Stan Gowen, Mark Richard Nutter, James Xenidis
  • Patent number: 7421453
    Abstract: Asynchronously traversing a disjoint linked data structure is presented. A synergistic processing unit (SPU) includes a handler that works in conjunction with a memory flow controller (MFC) to traverse a disjoint linked data structure. The handler compares a search value with a node value, and provides the MFC with an effective address of the next node to traverse based upon the comparison. In turn, the MFC retrieves the corresponding node data from system memory and stores the node data in the SPU's local storage area. The MFC stalls processing and sends an asynchronous event interrupt to the SPU which, as a result, instructs the handler to retrieve and compare the latest node data in the local storage area with the search value. The traversal continues until the handler matches the search value with a node value or until the handler determines a failed search.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: September 2, 2008
    Assignee: International Business Machines Corporation
    Inventors: Maximino Aguilar, Jr., Michael Norman Day, Mark Richard Nutter
  • Publication number: 20080209127
    Abstract: A system and method for an efficient implementation of a software-managed cache is presented. When an application thread executes on a simple processor, the application thread uses a conditional data select instruction for eliminating a conditional branch instruction when accessing a software-managed cache. An application thread issues a conditional data select instruction (DMA transfer) after a cache directory lookup, wherein the size of the requested data is dependent upon the outcome of the cache directory lookup. When the cache directory lookup results in a cache hit, the application thread requests a transfer of zero bits of data, which results in a DMA controller (DMAC) performing a no-op instruction. When the cache directory lookup results in a cache miss, the application thread requests a data block transfer the size of a corresponding cache line.
    Type: Application
    Filed: February 23, 2007
    Publication date: August 28, 2008
    Inventors: Daniel Alan Brokenshire, Michael Norman Day, Barry L. Minor, Mark Richard Nutter
  • Patent number: 7415703
    Abstract: A processing unit (PU) retrieves a file from system memory and loads it into its internal memory. The PU extracts a processor type from the file's header which identifies whether the file should execute on the PU or a synergistic processing unit (SPU). If an SPU should execute the file, the PU DMA's the file to the SPU for execution. In one embodiment, the file is a combined file which includes both PU and SPU code. In this embodiment, the PU identifies one or more section headers included in the file which indicates embedded SPU code within the combined file. In this embodiment, the PU extracts the SPU code from the combined file and DMA's the extracted code to an SPU for execution.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: August 19, 2008
    Assignee: International Business Machines Corporation
    Inventors: Maximino Aguilar, Jr., Alex Chunghen Chow, Michael Norman Day, Michael Stan Gowen, Mark Richard Nutter, James Xenidis
  • Publication number: 20080168443
    Abstract: An approach is provided to allow virtual devices that use a plurality of processors in a multiprocessor systems, such as the BE environment. Using this method, a synergistic processing unit (SPU) can either be dedicated to performing a particular function (i.e., audio, video, etc.) or a single SPU can be programmed to perform several functions on behalf of the other processors in the system. The application, preferably running in one of the primary (PU) processors, issues IOCTL commands through device drivers that correspond to SPUs. The kernel managing the primary processors responds by sending an appropriate message to the SPU that is performing the dedicated function. Using this method, an SPU can be virtualized for swapping multiple tasks or dedicated to performing a particular task.
    Type: Application
    Filed: March 14, 2008
    Publication date: July 10, 2008
    Inventors: Daniel Alan Brokenshire, Michael Norman Day, Barry L Minor, Mark Richard Nutter
  • Publication number: 20080163241
    Abstract: An approach that uses a handler to detect asynchronous lock line reservation lost events, and switching tasks based upon whether a condition is true or a mutex lock is acquired is presented. A synergistic processing unit (SPU) invokes a first thread and, during execution, the first thread requests external data that is shared with other threads or processors in the system. This shared data may be protected with a mutex lock or other shared memory synchronization constructs. When requested data is not available, the SPU switches to a second thread and monitors lock line reservation lost events in order to check when the data is available. When the data is available, the SPU switches back to the first thread and processes the first thread's request.
    Type: Application
    Filed: March 15, 2008
    Publication date: July 3, 2008
    Inventors: Maximino Aguilar, Michael Norman Day, Mark Richard Nutter
  • Publication number: 20080162834
    Abstract: A task queue manager manages the task queues corresponding to virtual devices. When a virtual device function is requested, the task queue manager determines whether an SPU is currently assigned to the virtual device task. If an SPU is already assigned, the request is queued in a task queue being read by the SPU. If an SPU has not been assigned, the task queue manager assigns one of the SPUs to the task queue. The queue manager assigns the task based upon which SPU is least busy as well as whether one of the SPUs recently performed the virtual device function. If an SPU recently performed the virtual device function, it is more likely that the code used to perform the function is still in the SPU's local memory and will not have to be retrieved from shared common memory using DMA operations.
    Type: Application
    Filed: March 15, 2008
    Publication date: July 3, 2008
    Inventors: Daniel Alan Brokenshire, Michael Norman Day, Barry L. Minor, Mark Richard Nutter, VanDung Dang To
  • Publication number: 20080155203
    Abstract: Grouping processors is presented. A processing unit (PU) initiates an application and identifies the application's requirements. The PU assigns one or more synergistic processing units (SPUs) and a memory space to the application in the form of a group. The application specifies whether the task requires shared memory or private memory. Shared memory is a memory space that is accessible by the SPUs and the PU. Private memory, however, is a memory space that is only accessible by the SPUs that are included in the group. When the application executes, the resources within the group are allocated to the application's execution thread. Each group has its own group properties, such as address space, policies (i.e. real-time, FIFO, run-to-completion, etc.) and priority (i.e. low or high). These group properties are used during thread execution to determine which groups take precedence over other tasks.
    Type: Application
    Filed: March 4, 2008
    Publication date: June 26, 2008
    Inventors: Maximino Aguilar, Michael Norman Day, Mark Richard Nutter, James Xenidis
  • Patent number: 7389508
    Abstract: A system and method for grouping processors is presented. A processing unit (PU) initiates an application and identifies the application's requirements. The PU assigns one or more synergistic processing units (SPUs) and a memory space to the application in the form of a group. The application specifies whether the task requires shared memory or private memory. Shared memory is a memory space that is accessible by the SPUs and the PU. Private memory, however, is a memory space that is only accessible by the SPUs that are included in the group. When the application executes, the resources within the group are allocated to the application's execution thread. Each group has its own group properties, such as address space, policies (i.e. real-time, FIFO, run-to-completion, etc.) and priority (i.e. low or high). These group properties are used during thread execution to determine which groups take precedence over other tasks.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: June 17, 2008
    Assignee: International Business Machines Corporation
    Inventors: Maximino Aguilar, Jr., Michael Norman Day, Mark Richard Nutter, James Xenidis
  • Publication number: 20080126817
    Abstract: A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode.
    Type: Application
    Filed: February 4, 2008
    Publication date: May 29, 2008
    Inventors: Shigehiro Asano, Jeffrey Douglas Brown, Michael Norman Day, Charles Ray Johns, James Allan Kahle, Alvan Wing Ng, Michael Fan Wang, Thuong Quang Truong
  • Patent number: 7363544
    Abstract: The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation of a main processor. A program operating in main memory halts due to operational errors. The program code lines save to a cache. In the main processor, a pool of memory is reserved. A copy of the data from the nominally inaccessible supplementary processor registers also transfers to the reserved storage area for processing of the program needing debugging. After the program debugging is complete, a copy of the contents of the memory pool is restored to the memory of the target supplemental processor. A copy of the local store register state and remaining local store data returns to main memory.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: April 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Michael Norman Day, Sidney James Manning