Patents by Inventor Nozomi Shimoishizaka

Nozomi Shimoishizaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11586175
    Abstract: A tool is equipped with a torque sensor, suited for a tightening task of a fastening component of a device such as a fluid control system that requires a large number of fastening components for assembly and has a narrow space for access to the fastening components, and capable of automatically detecting a tightening torque. The tool includes a torque sensor capable of detecting a tightening torque for tightening a fastening component acting on a bit. The torque sensor initiates measurement of the tightening torque when the tightening torque detected exceeds a set threshold value, completes measurement when the tightening torque detected falls below the set threshold value and a set time elapses, and outputs torque-related data formed on the basis of measurement data from measurement initiation to measurement completion and including a measurement time. The torque-related data includes a peak value of the measurement data.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: February 21, 2023
    Assignees: CONNECTEC JAPAN CORPORATION, FUJIKIN INCORPORATED
    Inventors: Kazutoshi Horikawa, Toru Nebashi, Hidekazu Machida, Nozomi Shimoishizaka, Akihiro Harada, Masahiko Ochiishi, Yoshiaki Yamato, Hiroki Karube, Mutsunori Koyomogi, Tsutomu Shinohara
  • Publication number: 20220310558
    Abstract: A manufacturing method comprises preparing a bonding substrate having bumps thereon; preparing a mounted member having external conductive members; applying a fixing material to the surface of the bonding substrate and/or to a surface of the mounted member; and fixing the bonding substrate and the mounted member with the fixing material such that the bumps contact the external conductive members. The fixing material is prepared to contain a first compound and a second compound, each having respective viscosities which change depending on their respective temperature profiles; and applying the fixing material to the bonding substrate and/or the mounted member at a temperature lower than a first temperature, and the fixing comprises pressing the bonding substrate against the mounted member when the fixing material has a temperature lower than the first temperature; and heating the fixing material to a temperature higher than the second temperature and curing the fixed material.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Inventors: Katsunori HIRATA, Nozomi SHIMOISHIZAKA, Takahiro NAKANO
  • Publication number: 20210278925
    Abstract: A technique is provided that is capable of obtaining image data for personal identification clearly in a short time at an arbitrary position in an area region at least about several times greater than a fingertip. In addition, a technique is provided that allows smooth progress of a series of process flow in a reservation site and an electronic commerce site for excellent user experience. An information processing system is provided that includes: an input section having a surface and configured to allow a user to contact or approximate a position specifier to the surface for information input; and a processing section configured to perform processing based on the information input to the input section, wherein the input section includes a position detection mechanism configured to detect a position of the position specifier on the surface and a reading mechanism configured to read biometric information of the user.
    Type: Application
    Filed: December 6, 2018
    Publication date: September 9, 2021
    Inventors: Hidekazu MACHIDA, Nozomi SHIMOISHIZAKA, Hiroshi KOMATSU
  • Publication number: 20200301401
    Abstract: A tool is equipped with a torque sensor, suited for a tightening task of a fastening component of a device such as a fluid control system that requires a large number of fastening components for assembly and has a narrow space for access to the fastening components, and capable of automatically detecting a tightening torque. The tool includes a torque sensor capable of detecting a tightening torque for tightening a fastening component acting on a bit. The torque sensor initiates measurement of the tightening torque when the tightening torque detected exceeds a set threshold value, completes measurement when the tightening torque detected falls below the set threshold value and a set time elapses, and outputs torque-related data formed on the basis of measurement data from measurement initiation to measurement completion and including a measurement time. The torque-related data includes a peak value of the measurement data.
    Type: Application
    Filed: December 3, 2018
    Publication date: September 24, 2020
    Applicants: CONNECTEC JAPAN Corporation, FUJIKIN INCORPORATED
    Inventors: Kazutoshi HORIKAWA, Toru NEBASHI, Hidekazu MACHIDA, Nozomi SHIMOISHIZAKA, Akihiro HARADA, Masahiko OCHIISHI, Yoshiaki YAMATO, Hiroki KARUBE, Mutsunori KOYOMOGI, Tsutomu SHINOHARA
  • Patent number: 8283775
    Abstract: A semiconductor device including a semiconductor element 1 having an active element region 1a, a plurality of element electrodes 2 formed on a principal face of the semiconductor element, external terminals 6 and 7 connected to one or more element electrodes via connection members 8 and 9, one or more first heat-dissipation protrusions 4 formed on the principal face of the semiconductor element, an insulation resin layer 10 covering the principal face of the semiconductor element and the first heat-dissipation protrusions, and a heat-dissipation medium 11 contacting a face of the insulation resin layer on a side opposite to a side contacting front faces of the first heat-dissipation protrusions.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: October 9, 2012
    Assignee: Panasonic Corporation
    Inventors: Nozomi Shimoishizaka, Yoshifumi Nakamura, Kouichi Nagao
  • Publication number: 20110163436
    Abstract: A semiconductor device including a semiconductor element 1 having an active element region 1a, a plurality of element electrodes 2 formed on a principal face of the semiconductor element, external terminals 6 and 7 connected to one or more element electrodes via connection members 8 and 9, one or more first heat-dissipation protrusions 4 formed on the principal face of the semiconductor element, an insulation resin layer 10 covering the principal face of the semiconductor element and the first heat-dissipation protrusions, and a heat-dissipation medium 11 contacting a face of the insulation resin layer on a side opposite to a side contacting front faces of the first heat-dissipation protrusions.
    Type: Application
    Filed: March 16, 2011
    Publication date: July 7, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Nozomi SHIMOISHIZAKA, Yoshifumi NAKAMURA, Kouichi NAGAO
  • Patent number: 7847198
    Abstract: A wiring board includes an insulating base; an adhesive layer formed on the surface of the insulating base; a conductor wiring formed on the surface of the adhesive layer; and a bump formed crossing the longitudinal direction of the conductor wiring over regions on the adhesive layer on both sides of the conductor wiring, wherein the back face at a part of the conductor wiring where the bump is formed, and the back faces and parts of the side faces of the bump formed above the regions of the adhesive layer on both sides of the conductor wiring, are embedded in the surface of the adhesive layer so as to be adhered to the adhesive layer. Even when the wiring width of the conductor wiring is decreased, the conductor wiring can be adhered to the wiring board firmly.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: December 7, 2010
    Assignee: Panasonic Corporation
    Inventors: Nozomi Shimoishizaka, Yoshifumi Nakamura
  • Patent number: 7800209
    Abstract: A wiring board includes a film base, a plurality of conductive wirings aligned on the film base, and protrusion electrodes formed of a plated metal in the vicinity of end portions of the conductive wirings, respectively. An outer surface at both side portions of the protrusion electrodes in cross section in a width direction of the conductive wirings defines a curve, and the protrusion electrodes in cross section in a longitudinal direction of the conductive wirings define a rectangular shape. The conductive wirings include a first conductive wiring having a wiring width of W1 and a second conductive wiring having a wiring width of W2 larger than W1, and the protrusion electrode on the first conductive wiring and the protrusion electrode on the second conductive wiring have a substantially same height.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Yukihiro Kozaka, Nozomi Shimoishizaka, Toshiyuki Fukuda
  • Patent number: 7800913
    Abstract: A wiring board includes: a flexible insulating base; a plurality of conductive wirings arranged on the insulating base, end portions of the conductive wirings defining inner leads at a region where a semiconductor chip is to be mounted; and bump electrodes that are provided respectively at the inner leads of the conductive wirings. The wiring board further includes: dummy inner leads having a shape and a pitch corresponding to a shape and a pitch of the inner leads and aligned with the inner leads, the dummy inner leads being provided with dummy bump electrodes corresponding to the bump electrodes; a trunk conductive wiring provided for a group of one or an adjacent plurality of the dummy inner leads; and a branch wiring branching off from the trunk conductive wiring, the branch wiring being connected with the dummy inner leads belonging to the group corresponding to the trunk conductive wiring.
    Type: Grant
    Filed: October 9, 2006
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Michiharu Torii, Kouichi Nagao, Nozomi Shimoishizaka
  • Patent number: 7772697
    Abstract: A semiconductor device includes a tape carrier substrate having a flexible insulating film base, a plurality of conductor wirings provided on the film base, and wiring bumps respectively formed so as to cover an upper surface and both side surfaces of the conductor wirings, and a semiconductor chip mounted on the tape carrier substrate, wherein electrodes of the semiconductor chip are connected to the conductor wirings via the wiring bumps. Electrode bumps are formed on the electrodes of the semiconductor chip, the electrodes of the semiconductor chip are connected to the conductor wirings via a bonding between the wiring bumps and the electrode bumps, and the electrode bumps are harder than the wiring bumps. This structure can reduce bonding damages to the electrodes of the semiconductor chip caused by a process of connecting the electrodes and the conductor wirings via the bumps.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: August 10, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazuhiko Matsumura, Nozomi Shimoishizaka
  • Patent number: 7629687
    Abstract: A semiconductor device includes a wiring board having a plurality of conductive wires aligned on an insulating base material and a board bump with a plated metal formed on each conductive wire so as to cover an upper surface and both sides of the conductive wire; and a semiconductor chip mounted on the wiring board, with electrodes of the semiconductor chip being connected to the conductive wires via the board bumps. Chip bumps are formed on the electrodes of the semiconductor chip. The electrodes of the semiconductor chip are connected to the conductive wires via a bond between the chip bumps and the board bumps. Protruding portions are formed by part of the plated metal of the board bumps at the bonded portion peeling off and protruding outwardly from a bonding surface of the chip bumps and the board bumps. Mechanical damage to the semiconductor chip caused by ultrasonic vibrations applied during process of mounting the semiconductor chip.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: December 8, 2009
    Assignee: Panasonic Corporation
    Inventors: Yukihiro Kozaka, Toshiyuki Fukuda, Nozomi Shimoishizaka, Kazuhiko Matsumura
  • Patent number: 7595222
    Abstract: The semiconductor device includes a first semiconductor chip having first electrodes on a fringe region of a main surface thereof, and a second semiconductor chip smaller in area than the first semiconductor chip and having second electrodes on a main surface thereof. The first semiconductor chip and the second semiconductor chip are connected together by bonding a surface of the second semiconductor chip that is opposite to the main surface thereof to a region of the main surface of the first semiconductor chip other than the fringe region. The first electrodes are connected to the second electrodes by wirings formed over the main surface of the first semiconductor chip, a side surface of the second semiconductor chip and the main surface of the second semiconductor chip.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: September 29, 2009
    Assignee: Panasonic Corporation
    Inventors: Nozomi Shimoishizaka, Toshiyuki Fukuda
  • Patent number: 7582968
    Abstract: A wiring board according to the present invention includes: an insulating base 22; a plurality of first conductor wirings 23a aligned in an inner region on the insulating base; bumps 24 formed on the respective first conductor wirings; and a protective film 25a that is formed on the insulating base so as to cover the first conductor wirings and has an opening region through which the bumps are exposed. The height of at least part of a surface of the protective film from a surface of the insulating base is greater than the height of the bumps from the surface of the insulating base. With this configuration, it is possible to decrease the thickness in the state where a protective tape is placed on the wiring board to protect bumps, thereby increasing the length of the wiring board that can be held by a reel for supplying the wiring board.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: September 1, 2009
    Assignee: Panasonic Corporation
    Inventors: Nozomi Shimoishizaka, Kouichi Nagao, Hiroyuki Imamura
  • Publication number: 20090154126
    Abstract: A wiring board includes a first bonding wiring array that is formed by extending conductor wirings, and that extends from an external side of a semiconductor element region and is bonded individually to a first element electrode array of a semiconductor element, and a second bonding wiring array that extends from the external side of the semiconductor element region and is bonded individually to a second element electrode array of the semiconductor element.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 18, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Nozomi SHIMOISHIZAKA, Kouichi NAGAO
  • Patent number: 7514802
    Abstract: A flexible insulating base, a plurality of conductor wirings aligned on the flexible insulating base, and bump electrodes provided respectively in end portions of the plurality of conductor wirings in a region where a semiconductor chip is to be placed are provided. The semiconductor chip is mounted on the conductor wirings by bonding electrode pads formed on the semiconductor chip to the bump electrodes. An auxiliary conductor wiring formed similarly to the conductor wirings is provided on the insulating base, and an auxiliary bump electrode formed similarly to the bump electrodes is provided on the auxiliary conductor wiring, so that the electrode pads formed on the semiconductor chip can be registered with respect to the bump electrodes on the conductor wirings by positioning the semiconductor chip with reference to the auxiliary bump electrode.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: April 7, 2009
    Assignee: Panasonic Corporation
    Inventors: Michinari Tetani, Takayuki Tanaka, Hiroyuki Imamura, Nozomi Shimoishizaka, Kouichi Nagao
  • Patent number: 7508073
    Abstract: A wiring board includes: an insulating substrate; a plurality of conductive wirings provided on the insulating substrate so as to be aligned with a semiconductor mounting region where a semiconductor chip is to be mounted; and bump electrodes provided on the respective conductive wirings. The bump electrodes include a first bump electrode for mounting the semiconductor chip and a second bump electrode for adjusting a height of the first bump electrode. The second bump electrode is provided at a region of at least one of the plurality of conductive wirings other than the semiconductor mounting region.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: March 24, 2009
    Assignee: Panasonic Corporation
    Inventors: Yoshifumi Nakamura, Nozomi Shimoishizaka
  • Publication number: 20090008771
    Abstract: Metal foil 1 is provided on a surface of a flexible substrate 4 so as to be thermally connected to a semiconductor chip 5, the surface being opposed to the other surface that is in contact with a radiator 2, and the metal foil 1 is screwed to the radiator 2 with fastening screws 3a. Thus heat generated from the semiconductor chip 5 is transmitted from one surface of the semiconductor chip 5 to the radiator 2 through a heat dissipating material 5b, and the heat is transmitted from the other surface of the semiconductor chip 5 to the radiator 2 through the metal foil 1, achieving heat transfer from the two surfaces of the semiconductor chip 5 to the radiator 2. Thus it is possible to improve heat dissipation without considerably increasing the number of components or a set weight.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 8, 2009
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Michiharu Torii, Nozomi Shimoishizaka
  • Patent number: 7442074
    Abstract: A wiring board includes first and second feeding electrodes (2, 3) provided along both sides of an insulating substrate (1), feeding bus lines (4) extending in a traverse direction and connected to both the feeding electrodes, and conductor wirings (6, 8, 12) having one side terminals forming inner leads having protruding electrodes (9, 11, 13) and the other side terminals connected to the feeding bus lines. The inner leads in each unit region are arranged in two lines extending in the traverse direction. The inner leads of a first group are arranged with a dense wiring pitch, and the inner leads of a second group include a dense pitch region in which a wiring pitch is the same as that of the inner leads of the first group, and a sparse pitch region in which a wiring pitch is longer than that of the inner leads of the first group.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: October 28, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Nozomi Shimoishizaka, Nobuyuki Koutani, Kouichi Nagao, Michiharu Torii, Yoshifumi Nakamura, Takayuki Tanaka
  • Publication number: 20080164608
    Abstract: A semiconductor device includes a tape carrier substrate having a flexible insulating film base, a plurality of conductor wirings provided on the film base, and wiring bumps respectively formed so as to cover an upper surface and both side surfaces of the conductor wirings, and a semiconductor chip mounted on the tape carrier substrate, wherein electrodes of the semiconductor chip are connected to the conductor wirings via the wiring bumps. Electrode bumps are formed on the electrodes of the semiconductor chip, the electrodes of the semiconductor chip are connected to the conductor wirings via a bonding between the wiring bumps and the electrode bumps, and the electrode bumps are harder than the wiring bumps. This structure can reduce bonding damages to the electrodes of the semiconductor chip caused by a process of connecting the electrodes and the conductor wirings via the bumps.
    Type: Application
    Filed: March 11, 2008
    Publication date: July 10, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Matsumura, Nozomi Shimoishizaka
  • Patent number: 7382050
    Abstract: A semiconductor device includes a tape carrier substrate having a flexible insulating film base, a plurality of conductor wirings provided on the film base, and wiring bumps respectively formed so as to cover an upper surface and both side surfaces of the conductor wirings, and a semiconductor chip mounted on the tape carrier substrate, wherein electrodes of the semiconductor chip are connected to the conductor wirings via the wiring bumps. Electrode bumps are formed on the electrodes of the semiconductor chip, the electrodes of the semiconductor chip are connected to the conductor wirings via a bonding between the wiring bumps and the electrode bumps, and the electrode bumps are harder than the wiring bumps. This structure can reduce bonding damages to the electrodes of the semiconductor chip caused by a process of connecting the electrodes and the conductor wirings via the bumps.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: June 3, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Matsumura, Nozomi Shimoishizaka