Patents by Inventor Nozomi Shimoishizaka
Nozomi Shimoishizaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7379307Abstract: A wiring board includes: an insulating base; a plurality of conductive wirings; and bumps formed on the conductive wirings, respectively. The conductive wirings can be connected with electrode pads of a semiconductor element via the bumps. The conductive wirings include a connection terminal portion at an end portion opposite to the other end portion where the bumps are formed, and at the connection terminal portion, the conductive wirings can be connected with an external component. The conductive wirings include first conductive wirings and second conductive wirings, on which the bumps are formed respectively at a semiconductor element mounting region. The first conductive wirings extend from the bumps to the connection terminal portion. The second conductive wirings extend beyond the semiconductor element mounting region from the bumps but do not reach the connection terminal portion.Type: GrantFiled: August 24, 2006Date of Patent: May 27, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroyuki Imamura, Nozomi Shimoishizaka
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Publication number: 20070284738Abstract: A wiring board includes an insulating base; an adhesive layer formed on the surface of the insulating base; a conductor wiring formed on the surface of the adhesive layer; and a bump formed crossing the longitudinal direction of the conductor wiring over regions on the adhesive layer on both sides of the conductor wiring, wherein the back face at a part of the conductor wiring where the bump is formed, and the back faces and parts of the side faces of the bump formed above the regions of the adhesive layer on both sides of the conductor wiring, are embedded in the surface of the adhesive layer so as to be adhered to the adhesive layer. Even when the wiring width of the conductor wiring is decreased, the conductor wiring can be adhered to the wiring board firmly.Type: ApplicationFiled: April 30, 2007Publication date: December 13, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Nozomi SHIMOISHIZAKA, Yoshifumi NAKAMURA
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Publication number: 20070241462Abstract: A wiring board includes: an insulating substrate; a plurality of conductive wirings provided on the insulating substrate so as to be aligned with a semiconductor mounting region where a semiconductor chip is to be mounted; and bump electrodes provided on the respective conductive wirings. The bump electrodes include a first bump electrode for mounting the semiconductor chip and a second bump electrode for adjusting a height of the first bump electrode. The second bump electrode is provided at a region of at least one of the plurality of conductive wirings other than the semiconductor mounting region.Type: ApplicationFiled: April 10, 2007Publication date: October 18, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yoshifumi NAKAMURA, Nozomi SHIMOISHIZAKA
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Patent number: 7279357Abstract: A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.Type: GrantFiled: May 5, 2005Date of Patent: October 9, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Kazuyuki Kaino, Yoshifumi Nakamura, Keiji Miki, Kazumi Watase, Ryuichi Sahara
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Publication number: 20070182009Abstract: A wiring board includes a film base, a plurality of conductive wirings aligned on the film base, and protrusion electrodes formed of a plated metal in the vicinity of end portions of the conductive wirings, respectively. An outer surface at both side portions of the protrusion electrodes in cross section in a width direction of the conductive wirings defines a curve, and the protrusion electrodes in cross section in a longitudinal direction of the conductive wirings define a rectangular shape. The conductive wirings include a first conductive wiring having a wiring width of W1 and a second conductive wiring having a wiring width of W2 larger than W1, and the protrusion electrode on the first conductive wiring and the protrusion electrode on the second conductive wiring have a substantially same height.Type: ApplicationFiled: January 8, 2007Publication date: August 9, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yukihiro KOZAKA, Nozomi SHIMOISHIZAKA, Toshiyuki FUKUDA
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Publication number: 20070120235Abstract: A wiring board according to the present invention includes: an insulating base 22; a plurality of first conductor wirings 23a aligned in an inner region on the insulating base; bumps 24 formed on the respective first conductor wirings; and a protective film 25a that is formed on the insulating base so as to cover the first conductor wirings and has an opening region through which the bumps are exposed. The height of at least part of a surface of the protective film from a surface of the insulating base is greater than the height of the bumps from the surface of the insulating base. With this configuration, it is possible to decrease the thickness in the state where a protective tape is placed on the wiring board to protect bumps, thereby increasing the length of the wiring board that can be held by a reel for supplying the wiring board.Type: ApplicationFiled: November 10, 2006Publication date: May 31, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Nozomi Shimoishizaka, Kouichi Nagao, Hiroyuki Imamura
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Publication number: 20070119614Abstract: A wiring board includes first and second feeding electrodes (2, 3) provided along both sides of an insulating substrate (1), feeding bus lines (4) extending in a traverse direction and connected to both the feeding electrodes, and conductor wirings (6, 8, 12) having one side terminals forming inner leads having protruding electrodes (9, 11, 13) and the other side terminals connected to the feeding bus lines. The inner leads in each unit region are arranged in two lines extending in the traverse direction. The inner leads of a first group are arranged with a dense wiring pitch, and the inner leads of a second group include a dense pitch region in which a wiring pitch is the same as that of the inner leads of the first group, and a sparse pitch region in which a wiring pitch is longer than that of the inner leads of the first group.Type: ApplicationFiled: November 10, 2006Publication date: May 31, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Nozomi SHIMOISHIZAKA, Nobuyuki KOUTANI, Kouichi NAGAO, Michiharu TORII, Yoshifumi NAKAMURA, Takayuki TANAKA
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Publication number: 20070108627Abstract: A semiconductor device includes a wiring board having a plurality of conductive wires aligned on an insulating base material and a board bump with a plated metal formed on each conductive wire so as to cover an upper surface and both sides of the conductive wire; and a semiconductor chip mounted on the wiring board, with electrodes of the semiconductor chip being connected to the conductive wires via the board bumps. Chip bumps are formed on the electrodes of the semiconductor chip. The electrodes of the semiconductor chip are connected to the conductive wires via a bond between the chip bumps and the board bumps. Protruding portions are formed by part of the plated metal of the board bumps at the bonded portion peeling off and protruding outwardly from a bonding surface of the chip bumps and the board bumps. Mechanical damage to the semiconductor chip caused by ultrasonic vibrations applied during process of mounting the semiconductor chip.Type: ApplicationFiled: October 27, 2006Publication date: May 17, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yukihiro KOZAKA, Toshiyuki FUKUDA, Nozomi SHIMOISHIZAKA, Kazuhiko MATSUMURA
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Publication number: 20070109759Abstract: A wiring board includes: a flexible insulating base; a plurality of conductive wirings arranged on the insulating base, end portions of the conductive wirings defining inner leads at a region where a semiconductor chip is to be mounted; and bump electrodes that are provided respectively at the inner leads of the conductive wirings. The wiring board further includes: dummy inner leads having a shape and a pitch corresponding to a shape and a pitch of the inner leads and aligned with the inner leads, the dummy inner leads being provided with dummy bump electrodes corresponding to the bump electrodes; a trunk conductive wiring provided for a group of one or an adjacent plurality of the dummy inner leads; and a branch wiring branching off from the trunk conductive wiring, the branch wiring being connected with the dummy inner leads belonging to the group corresponding to the trunk conductive wiring.Type: ApplicationFiled: October 9, 2006Publication date: May 17, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Michiharu TORII, Kouichi NAGAO, Nozomi SHIMOISHIZAKA
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Publication number: 20070075426Abstract: A flexible insulating base, a plurality of conductor wirings aligned on the flexible insulating base, and bump electrodes provided respectively in end portions of the plurality of conductor wirings in a region where a semiconductor chip is to be placed are provided. The semiconductor chip is mounted on the conductor wirings by bonding electrode pads formed on the semiconductor chip to the bump electrodes. An auxiliary conductor wiring formed similarly to the conductor wirings is provided on the insulating base, and an auxiliary bump electrode formed similarly to the bump electrodes is provided on the auxiliary conductor wiring, so that the electrode pads formed on the semiconductor chip can be registered with respect to the bump electrodes on the conductor wirings by positioning the semiconductor chip with reference to the auxiliary bump electrode.Type: ApplicationFiled: September 13, 2006Publication date: April 5, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Michinari TETANI, Takayuki TANAKA, Hiroyuki IMAMURA, Nozomi SHIMOISHIZAKA, Kouichi NAGAO
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Publication number: 20070057369Abstract: A wiring board includes: an insulating base; a plurality of conductive wirings; and bumps formed on the conductive wirings, respectively. The conductive wirings can be connected with electrode pads of a semiconductor element via the bumps. The conductive wirings include a connection terminal portion at an end portion opposite to the other end portion where the bumps are formed, and at the connection terminal portion, the conductive wirings can be connected with an external component. The conductive wirings include first conductive wirings and second conductive wirings, on which the bumps are formed respectively at a semiconductor element mounting region. The first conductive wirings extend from the bumps to the connection terminal portion. The second conductive wirings extend beyond the semiconductor element mounting region from the bumps but do not reach the connection terminal portion.Type: ApplicationFiled: August 24, 2006Publication date: March 15, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hiroyuki IMAMURA, Nozomi SHIMOISHIZAKA
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Publication number: 20060237841Abstract: A semiconductor device includes a tape carrier substrate having a flexible insulating film base, a plurality of conductor wirings provided on the film base, and wiring bumps respectively formed so as to cover an upper surface and both side surfaces of the conductor wirings, and a semiconductor chip mounted on the tape carrier substrate, wherein electrodes of the semiconductor chip are connected to the conductor wirings via the wiring bumps. Electrode bumps are formed on the electrodes of the semiconductor chip, the electrodes of the semiconductor chip are connected to the conductor wirings via a bonding between the wiring bumps and the electrode bumps, and the electrode bumps are harder than the wiring bumps. This structure can reduce bonding damages to the electrodes of the semiconductor chip caused by a process of connecting the electrodes and the conductor wirings via the bumps.Type: ApplicationFiled: April 17, 2006Publication date: October 26, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kazuhiko Matsumura, Nozomi Shimoishizaka
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Patent number: 6954001Abstract: The semiconductor device includes a semiconductor element having an electrode formed on a surface thereof, and a metal wiring formed on the surface of the semiconductor element and electrically connected to the electrode. The metal wiring has an external electrode portion functioning as an external electrode. A thickness of the external electrode portion is greater than that of a non-electrode portion of the metal wiring, i.e., a portion of the metal wiring other than the external electrode portion.Type: GrantFiled: August 17, 2004Date of Patent: October 11, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshifumi Nakamura, Ryuichi Sahara, Nozomi Shimoishizaka, Kazuyuki Kainou, Keiji Miki, Kazumi Watase, Yasutake Yaguchi
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Publication number: 20050199979Abstract: A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.Type: ApplicationFiled: May 5, 2005Publication date: September 15, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Kazuyuki Kaino, Yoshifumi Nakamura, Keiji Miki, Kazumi Watase, Ryuichi Sahara
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Patent number: 6924173Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.Type: GrantFiled: March 14, 2003Date of Patent: August 2, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazumi Watase, Hiroaki Fujimoto, Ryuichi Sahara, Nozomi Shimoishizaka, Takahiro Kumakawa, Kazuyuki Kaino, Yoshifumi Nakamura
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Publication number: 20050146005Abstract: The semiconductor device includes a first semiconductor chip having first electrodes on a fringe region of a main surface thereof, and a second semiconductor chip smaller in area than the first semiconductor chip and having second electrodes on a main surface thereof. The first semiconductor chip and the second semiconductor chip are connected together by bonding a surface of the second semiconductor chip that is opposite to the main surface thereof to a region of the main surface of the first semiconductor chip other than the fringe region. The first electrodes are connected to the second electrodes by wirings formed over the main surface of the first semiconductor chip, a side surface of the second semiconductor chip and the main surface of the second semiconductor chip.Type: ApplicationFiled: February 15, 2005Publication date: July 7, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Toshiyuki Fukuda
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Patent number: 6914331Abstract: A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.Type: GrantFiled: May 21, 2003Date of Patent: July 5, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Kazuyuki Kaino, Yoshifumi Nakamura, Keiji Miki, Kazumi Watase, Ryuichi Sahara
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Patent number: 6852616Abstract: A first element electrode and a second element electrode connected electrically to a semiconductor element on a substrate are formed, and then an insulating film is formed on the substrate including the element electrodes. Thereafter, a first opening for exposing the first element electrode and a second opening for exposing the second element electrode are formed on the insulating film. Then, a first external electrode connected to the first element electrode via the first opening is formed immediately above the first element electrode. Furthermore, a second external electrode and a connecting wire having one end connected to the second element electrode via the second opening and the other end connected to the second external electrode are formed on the insulating film.Type: GrantFiled: June 10, 2002Date of Patent: February 8, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ryuichi Sahara, Kazumi Watase, Takahiro Kumakawa, Kazuyuki Kainoh, Nozomi Shimoishizaka
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Publication number: 20050012214Abstract: The semiconductor device includes a semiconductor element having an electrode formed on a surface thereof, and a metal wiring formed on the surface of the semiconductor element and electrically connected to the electrode. The metal wiring has an external electrode portion functioning as an external electrode. A thickness of the external electrode portion is greater than that of a non-electrode portion of the metal wiring, i.e., a portion of the metal wiring other than the external electrode portion.Type: ApplicationFiled: August 17, 2004Publication date: January 20, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yoshifumi Nakamura, Ryuichi Sahara, Nozomi Shimoishizaka, Kazuyuki Kainou, Keiji Miki, Kazumi Watase, Yasutake Yaguchi
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Publication number: 20050006749Abstract: A low elasticity layer (20) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate (10). On the low elasticity layer (20), lands (32) serving as external electrodes are disposed, and pads (30) on the element electrodes, the lands (32) and metal wires (31) for connecting them are integrally formed as a metal wiring pattern (33). A solder resist film (50) having an opening for exposing a part of each land (32) is formed, and a metal ball (40) is provided on the land (32) in the opening. The low elasticity layer (20) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires (31).Type: ApplicationFiled: August 12, 2004Publication date: January 13, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Nozomi Shimoishizaka, Ryuichi Sahara, Yoshifumi Nakamura, Takahiro Kumakawa, Shinji Murakami, Yutaka Harada