Patents by Inventor Nozomu Matsuzaki
Nozomu Matsuzaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050237805Abstract: A semiconductor non-volatile storage device of the present invention which lets a memory cell directly drive up to a local bit line, wherein the output of the local bit line is received by a gate electrode of a separately-provided signal amplifying transistor, and the signal amplifying transistor is used to drive a global bit line having a large load capacity. Since an amplifying transistor having a drive power higher than a memory cell drives the parasitic capacity of a global bit line, information stored in a memory cell can be read out at high speed. Therefore, the storage device is used for storing program codes for controlling microcomputers or the like to thereby enhance a system performance.Type: ApplicationFiled: June 21, 2005Publication date: October 27, 2005Inventors: Nozomu Matsuzaki, Hideaki Kurata, Takayuki Kawahara
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Patent number: 6944056Abstract: A semiconductor non-volatile storage device of the present invention which lets a memory cell directly drive up to a local bit line, wherein the output of the local bit line is received by a gate electrode of a separately-provided signal amplifying transistor, and the signal amplifying transistor is used to drive a global bit line having a large load capacity. Since an amplifying transistor having a drive power higher than a memory cell drives the parasitic capacity of a global bit line, information stored in a memory cell can be read out at high speed. Therefore, the storage device is used for storing program codes for controlling microcomputers or the like to thereby enhance a system performance.Type: GrantFiled: April 2, 2001Date of Patent: September 13, 2005Assignee: Renesas Technology Corp.Inventors: Nozomu Matsuzaki, Hideaki Kurata, Takayuki Kawahara
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Publication number: 20050189579Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: April 18, 2005Publication date: September 1, 2005Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20050190608Abstract: The present invention is drawn to a semiconductor integrated circuit device employing employs on the same silicon substrate a plurality of kinds of MOS transistors with different in magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.Type: ApplicationFiled: May 2, 2005Publication date: September 1, 2005Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
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Publication number: 20050185445Abstract: A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.Type: ApplicationFiled: February 15, 2005Publication date: August 25, 2005Inventors: Kenichi Osada, Riichiro Takemura, Norikatsu Takaura, Nozomu Matsuzaki, Takayuki Kawahara
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Publication number: 20050090058Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: September 30, 2004Publication date: April 28, 2005Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Patent number: 6862220Abstract: A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.Type: GrantFiled: July 9, 2004Date of Patent: March 1, 2005Assignee: Renesas Technology CorporationInventors: Takayuki Kawahara, Nozomu Matsuzaki, Terumi Sawase, Masaharu Kubo
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Publication number: 20050006698Abstract: Memory cells in which an erase and write operation is performed by injecting electrons from a substrate and extracting the electrons into a gate electrode constitute a semiconductor nonvolatile memory device. That is a gate extraction semiconductor nonvolatile memory device. In that device, if an erase bias is applied in a first process of an erase and write operation, memory cells in an overerase condition occur and the charge retention characteristics of such memory cells are degraded. The present invention provides a semiconductor nonvolatile memory device using means for writing all the memory cells in an erase unit before applying the erase bias, and then applying the erase bias.Type: ApplicationFiled: May 25, 2004Publication date: January 13, 2005Inventors: Nozomu Matsuzaki, Tetsuya Ishimaru, Makoto Mizuno, Takashi Hashimoto
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Patent number: 6842376Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.Type: GrantFiled: August 12, 2003Date of Patent: January 11, 2005Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
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Patent number: 6833582Abstract: A nonvolatile semiconductor memory device configured by a select MOS transistor provided with a gate insulator film and a select gate electrode, as well as a memory MOS transistor provided with a capacitor insulator film comprising a lower potential barrier film, a charge trapping film, and an upper potential barrier film, as well as a memory gate electrode. The charge trapping film is formed with a silicon oxynitride film and the upper potential barrier film is omitted or its thickness is limited to 1 nm and under to prevent the Gm degradation to be caused by the silicon oxynitride film, thereby lowering the erasure gate voltage. The charge trapping film is formed with a silicon oxynitride film used as a main charge trapping film and a silicon nitride film formed on or beneath the silicon oxynitride film so as to form a potential barrier effective only for holes. And, a hot-hole erasing method is employed to lower the erasure voltage.Type: GrantFiled: January 29, 2004Date of Patent: December 21, 2004Assignee: Renesas Technology Corp.Inventors: Toshiyuki Mine, Takashi Hashimoto, Senichi Nishibe, Nozomu Matsuzaki, Hitoshi Kume, Jiro Yugami
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Publication number: 20040253788Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistor can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: May 24, 2004Publication date: December 16, 2004Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20040246780Abstract: A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.Type: ApplicationFiled: July 9, 2004Publication date: December 9, 2004Applicant: Renesas Technology Corp.Inventors: Takayuki Kawahara, Nozomu Matsuzaki, Terumi Sawase, Masaharu Kubo
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Publication number: 20040183122Abstract: A nonvolatile semiconductor memory device configured by a select MOS transistor provided with a gate insulator film and a select gate electrode, as well as a memory MOS transistor provided with a capacitor insulator film comprising a lower potential barrier film, a charge trapping film, and an upper potential barrier film, as well as a memory gate electrode. The charge trapping film is formed with a silicon oxynitride film and the upper potential barrier film is omitted or its thickness is limited to 1 nm and under to prevent the Gm degradation to be caused by the silicon oxynitride film, thereby lowering the erasure gate voltage. The charge trapping film is formed with a silicon oxynitride film used as a main charge trapping film and a silicon nitride film formed on or beneath the silicon oxynitride film so as to form a potential barrier effective only for holes. And, a hot-hole erasing method is employed to lower the erasure voltage.Type: ApplicationFiled: January 29, 2004Publication date: September 23, 2004Applicant: Renesas Technology Corp.Inventors: Toshiyuki Mine, Takashi Hashimoto, Senichi Nishibe, Nozomu Matsuzaki, Hitoshi Kume, Jiro Yugami
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Patent number: 6785165Abstract: A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.Type: GrantFiled: December 4, 2002Date of Patent: August 31, 2004Assignee: Renesas Technology CorporationInventors: Takayuki Kawahara, Nozomu Matsuzaki, Terumi Sawase, Masaharu Kubo
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Publication number: 20040155234Abstract: Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder.Type: ApplicationFiled: December 24, 2003Publication date: August 12, 2004Applicant: Renesas Technology Corp.Inventors: Tetsuya Ishimaru, Nozomu Matsuzaki, Hitoshi Kume
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Publication number: 20040140485Abstract: A semiconductor non-volatile storage device of the present invention which lets a memory cell directly drive up to a local bit line, wherein the output of the local bit line is received by a gate electrode of a separately-provided signal amplifying transistor, and the signal amplifying transistor is used t drive a global bit line having a large load capacity. Since an amplifying transistor having a drive power higher than a memory cell drives the parasitic capacity of a global bit line, information stored in a memory cell can be read out at high speed. Therefore, the storage device is used for storing program codes for controlling microcomputers or the like to thereby enhance a system performance.Type: ApplicationFiled: October 2, 2003Publication date: July 22, 2004Inventors: Nozomu Matsuzaki, Hideaki Kurata, Takayuki Kawahara
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Publication number: 20040119107Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on the both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.Type: ApplicationFiled: December 4, 2003Publication date: June 24, 2004Inventors: Digh Hisamoto, Shinichiro Kimura, Kan Yasui, Nozomu Matsuzaki
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Patent number: 6711061Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.Type: GrantFiled: August 20, 2002Date of Patent: March 23, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
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Publication number: 20040047223Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.Type: ApplicationFiled: August 12, 2003Publication date: March 11, 2004Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
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Semiconductor device having groove isolation structure and gate oxide films with different thickness
Patent number: 6657248Abstract: There was a problem that sharpening of a substrate and localized increase in the thickness of a gate oxide film become more remarkable as the thickness of the gate oxide film is increased to degrade the gate withstand voltage at the surface edge of shallow groove isolation structure. In the present invention, a bird's beak is disposed at the surface edge of a shallow isolation structure GROX11 just below gate electrode POLY11 and in contact with the gate insulation film HOX1 to form the gate insulation film HOX1 previously. This can ensure normal gate withstand voltage of the MOS transistor and favorable device isolation withstand voltage and increased integration degree simultaneously.Type: GrantFiled: November 2, 1999Date of Patent: December 2, 2003Assignee: Hitachi, Ltd.Inventors: Nozomu Matsuzaki, Takashi Kobayashi, Hitoshi Kume, Toshiyuki Mine, Kikuo Kusukawa, Norio Suzuki, Kenji Takahashi, Toshiaki Nishimoto, Masataka Kato