Patents by Inventor Nozomu Matsuzaki
Nozomu Matsuzaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6617632Abstract: A parallel connection-type nonvolatile memory semiconductor device comprises a plurality of memory cells disposed on a semiconductor substrate in matrix form, each including a gate insulating film, a floating gate electrode, an interlayer film and a control gate electrode successively formed so as to cover a channel region on a main surface of the semiconductor substrate, of a first conductivity type; a second conductivity type source and drain regions formed on the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween; a first semiconductor region which is adjacent to the drain region and formed by introducing a second conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially lower than the drain region in impurity concentration; and a punch-thType: GrantFiled: December 7, 2001Date of Patent: September 9, 2003Assignee: Hitachi, Ltd.Inventors: Yasuhiro Taniguchi, Kazuyoshi Shiba, Nozomu Matsuzaki, Hidenori Takada, Hitoshi Kume, Shoji Shukuri
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Publication number: 20030148583Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: February 27, 2003Publication date: August 7, 2003Inventors: Tetsuo Adachi, Masataka Kato, Toshiaki Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20030142550Abstract: A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.Type: ApplicationFiled: December 4, 2002Publication date: July 31, 2003Applicant: Hitachi, Ltd.Inventors: Takayuki Kawahara, Nozomu Matsuzaki, Terumi Sawase, Masaharu Kubo
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Publication number: 20030052371Abstract: The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units.Type: ApplicationFiled: October 4, 2002Publication date: March 20, 2003Applicant: Hitachi, Ltd.Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
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Publication number: 20030012052Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.Type: ApplicationFiled: August 20, 2002Publication date: January 16, 2003Applicant: Hitachi, Ltd. and Hitachi ULSI Systems Co., Ltd.Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
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Patent number: 6500715Abstract: The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units.Type: GrantFiled: May 11, 2001Date of Patent: December 31, 2002Assignee: Hitachi, Ltd.Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
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Publication number: 20020192887Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: June 18, 2002Publication date: December 19, 2002Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Patent number: 6461916Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: GrantFiled: February 7, 2000Date of Patent: October 8, 2002Assignee: Hitachi, Ltd.Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Patent number: 6459619Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for-each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.Type: GrantFiled: November 7, 2001Date of Patent: October 1, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
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Patent number: 6444554Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: GrantFiled: December 11, 2001Date of Patent: September 3, 2002Assignee: Hitachi, Ltd.Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20020074569Abstract: A parallel connection-type nonvolatile memory semiconductor device comprises a plurality of memory cells disposed on a semiconductor substrate in matrix form, each including a gate insulating film, a floating gate electrode, an interlayer film and a control gate electrode successively formed so as to cover a channel region on a main surface of the semiconductor substrate, of a first conductivity type; a second conductivity type source and drain regions formed on the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween; a first semiconductor region which is adjacent to the drain region and formed by introducing a second conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially lower than the drain region in impurity concentration; and a punch-thType: ApplicationFiled: December 7, 2001Publication date: June 20, 2002Applicant: Assignee: Hitachi, Ltd.Inventors: Yasuhiro Taniguchi, Kazuyoshi Shiba, Nozomu Matsuzaki, Hidenori Takada, Hitoshi Kume, Shoji Shukuri
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Publication number: 20020064898Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.Type: ApplicationFiled: December 11, 2001Publication date: May 30, 2002Inventors: Tetsuo Adachi, Masataka Kato, Toshiakl Nishimoto, Nozomu Matsuzaki, Takashi Kobayashi, Yoshimi Sudou, Toshiyuki Mine
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Publication number: 20020054510Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.Type: ApplicationFiled: November 7, 2001Publication date: May 9, 2002Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
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Publication number: 20010034093Abstract: The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units.Type: ApplicationFiled: May 11, 2001Publication date: October 25, 2001Applicant: Hitachi, Ltd.Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
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Patent number: 6307236Abstract: The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units.Type: GrantFiled: October 6, 1998Date of Patent: October 23, 2001Assignee: Hitachi, Ltd.Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
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Patent number: 5680066Abstract: A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplituType: GrantFiled: January 13, 1994Date of Patent: October 21, 1997Assignee: Hitachi, Ltd.Inventors: Takashi Akioka, Masahiro Iwamura, Atsushi Hiraishi, Yuji Yokoyama, Nozomu Matsuzaki, Tatsumi Yamauchi, Yutaka Kobayashi, Nobuyuki Gotou, Akira Ide, Masahiro Yamamura, Hideaki Uchida
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Patent number: 5619151Abstract: A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; aType: GrantFiled: June 7, 1995Date of Patent: April 8, 1997Assignee: Hitachi, Ltd.Inventors: Takashi Akioka, Masahiro Iwamura, Atsushi Hiraishi, Yuji Yokoyama, Nozomu Matsuzaki, Tatsumi Yamauchi, Yutaka Kobayashi, Nobuyuki Gotou, Akira ide, Masahiro Yamamura, Hideaki Uchida
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Patent number: 5091883Abstract: An input buffer for processing an external signal is provided in one of passways, which is the most closest to a line for equally dividing the whole of a plurality of memory cell blocks longitudinally or laterally into two sections, the passway interposing between the adjacent memory cell blocks of the plurality of memory cell blocks to which a processed signal of the input buffer is transmitted, whereby the length of the signal pass from the input buffer to each memory cell of the memory cell blocks can be shortened. Therefore, since the memory cell or a logic element existing between the input buffer and the memory cell is operated by a pulse of little distortion without delay of time, a access time can be reduced and a processing speed of a microprocessor can be increased. Further, a degree of freedom in designing a system of a memory or the microprocessor is further improved.Type: GrantFiled: July 13, 1990Date of Patent: February 25, 1992Assignee: Hitachi, Ltd.Inventors: Nozomu Matsuzaki, Takashi Akioka, Masahiro Iwamura, Atushi Hiraishi, Tatsumi Yamauchi, Yuji Yokoyama, Yutaka Kobayashi, Hideaki Uchida