Abstract: Aspects of the present disclosure are directed to decoding signals susceptible to communication errors. As may be implemented in accordance with one or more embodiments, an input signal is decoded to produce a first decoded output, which is subsequently encoded, and error characteristics of the encoded first decoded output are assessed. The input signal is again decoded (e.g., with a delay), using the encoded first decoded output and the assessed error characteristics thereof to assess a reliability characteristic of bits in the input signal. A second decoded output is then provided with errors corrected therein based on the assessed reliability characteristic.

Abstract: Aspects of the present disclosure are directed to decoding signals susceptible to communication errors. As may be implemented in accordance with one or more embodiments, an input signal is decoded to produce a first decoded output, which is subsequently encoded, and error characteristics of the encoded first decoded output are assessed. The input signal is again decoded (e.g., with a delay), using the encoded first decoded output and the assessed error characteristics thereof to assess a reliability characteristic of bits in the input signal. A second decoded output is then provided with errors corrected therein based on the assessed reliability characteristic.

Abstract: In accordance with an embodiment of the invention, an IC device is disclosed. In the embodiment, the IC device includes an array of bit cells of static random-access memory (SRAM), a multi-level digitization module configured to generate a value in a range of values from a bit cell in the array of bit cells, the range of values including more than two discrete values, an output buffer configured to store the generated values, and an error correction code (ECC) decoder configured to output error corrected values based on the stored values.

Abstract: In accordance with an embodiment of the invention, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an SRAM module, wrapper logic coupled to the SRAM module, a context source, and an ECC profile controller coupled to the context source and to the wrapper logic, the ECC profile controller configured to select an ECC profile in response to context information received from the context source for use by the wrapper logic.

Abstract: A wireless receiver for a distributed antenna diversity receiver apparatus comprising a pre-combining component arranged to receive an RF signal from an antenna and to recover and output an information signal contained within the received RF signal, and a combined-signal component arranged to receive the recovered information signal output by the pre-combining component of the wireless receiver and a further recovered information signal from a further wireless receiver and to perform diversity combining of the recovered information signals to obtain and output an enhanced information signal. The wireless receiver further comprises a monitoring component arranged to receive intra-packet channel reliability parameters for the wireless receiver and for the further wireless receiver, determine whether to assign a new master receiver for the distributed antenna diversity receiver apparatus based on the received intra-packet reliability parameters.

Abstract: A receiver for a modulated signal of a communication system is disclosed. The receiver includes a demodulator to demodulate the received modulated symbols of a received signal into received soft-bits. The receiver also includes a hard-decision decoder that is configured to decode the received soft-bits into decoded bits. A feedback loop is included to provide feedback from the hard decision decoder to the demodulator. The feedback loop is configured to re-encode the decoded bits from the hard-decision decoder into re-encoded bits. The demodulator is further configured to iteratively demodulate the received modulated signal using an output of the feedback loop.

Abstract: A wireless receiver for a distributed antenna diversity receiver apparatus comprising a pre-combining component arranged to receive an RF signal from an antenna and to recover and output an information signal contained within the received RF signal, and a combined-signal component arranged to receive the recovered information signal output by the pre-combining component of the wireless receiver and a further recovered information signal from a further wireless receiver and to perform diversity combining of the recovered information signals to obtain and output an enhanced information signal. The wireless receiver further comprises a monitoring component arranged to receive intra-packet channel reliability parameters for the wireless receiver and for the further wireless receiver, determine whether to assign a new master receiver for the distributed antenna diversity receiver apparatus based on the received intra-packet reliability parameters.

Abstract: Receivers and methods of operation are described. A receiver for a modulated signal of a communication system, comprises a demodulator to demodulate the received modulated symbols of a received signal into received soft-bits. A hard-decision decoder is arranged and configured to decode the received soft-bits into decoded bits. A feedback loop is arranged to provide feedback from the hard decision decoder to the demodulator. the feedback loop is configured to re-encode the decoded bits from the hard-decision decoder into re-encoded bits. The demodulator is further arranged and configured to iteratively demodulate the received modulated signal using an output of the feedback loop.

Abstract: A signal processing circuit comprising a clip-generation-block. The clip-generation-block is configured to receive an input-signal; and determine a clip-signal that comprises only values of the input-signal that exceed a clipping-threshold. The signal processing circuit also comprises a scaling-block configured to apply a scaling-factor to the clip-signal in order to generate a scaled-clip-signal, wherein the scaling-factor is greater than one; and an adder configured to provide a clipped-signal based on a difference between the scaled-clip-signal and the input signal.

Abstract: A signal processing circuit comprising a clip-generation-block. The clip-generation-block is configured to receive an input-signal; and determine a clip-signal that comprises only values of the input-signal that exceed a clipping-threshold. The signal processing circuit also comprises a scaling-block configured to apply a scaling-factor to the clip-signal in order to generate a scaled-clip-signal, wherein the scaling-factor is greater than one; and an adder configured to provide a clipped-signal based on a difference between the scaled-clip-signal and the input signal.

Abstract: An integrated circuit (IC) device including an SRAM module coupled to wrapper logic is disclosed. The wrapper logic includes an error correction code (ECC) encoder configured to encode input data in accordance with an ECC encoding scheme and output the encoded input data to the SRAM module, an ECC decoder configured to decode output data received from the SRAM module, output the decoded output data, and write decoding information back to the SRAM module, an error controller coupled to the ECC decoder that is configured to control the ECC decoder in accordance with the ECC encoding scheme, and a central controller coupled to the components of the wrapper logic and the SRAM module in order to control operations between the components of the wrapper logic and the SRAM module.

Abstract: An integrated circuit (IC) device including an SRAM module coupled to wrapper logic is disclosed. The wrapper logic includes an error correction code (ECC) encoder configured to encode input data in accordance with an ECC encoding scheme and output the encoded input data to the SRAM module, an ECC decoder configured to decode output data received from the SRAM module, output the decoded output data, and write decoding information back to the SRAM module, an error controller coupled to the ECC decoder that is configured to control the ECC decoder in accordance with the ECC encoding scheme, and a central controller coupled to the components of the wrapper logic and the SRAM module in order to control operations between the components of the wrapper logic and the SRAM module.

Abstract: In accordance with an embodiment of the invention, an IC device is disclosed. In the embodiment, the IC device includes an array of bit cells of static random-access memory (SRAM), a multi-level digitization module configured to generate a value in a range of values from a bit cell in the array of bit cells, the range of values including more than two discrete values, an output buffer configured to store the generated values, and an error correction code (ECC) decoder configured to output error corrected values based on the stored values.

Abstract: In accordance with an embodiment of the invention, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an SRAM module, wrapper logic coupled to the SRAM module, a context source, and an ECC profile controller coupled to the context source and to the wrapper logic, the ECC profile controller configured to select an ECC profile in response to context information received from the context source for use by the wrapper logic.

Abstract: A receiver, including: a posteriori probability demodulator configured to receive an input digital signal and output demodulated data; a deinterleaver configured to deinterleave the demodulated data; a forward error correction (FEC) decoder configured to error correct the demodulated data; a FEC encoder configured to encode the error corrected demodulated data; an interleaver configured to interleave the FEC encoded data and output the interleaved FEC encoded data to the posteriori probability demodulator; and a symbol compressor/decompressor configured to compress symbol data from the a posteriori demodulator and store the compressed data in a symbol memory and configured to decompress compressed symbol data stored in the symbol memory.

Abstract: A receiver, including: a posteriori probability demodulator configured to receive an input digital signal and output demodulated data; a deinterleaver configured to deinterleave the demodulated data; a forward error correction (FEC) decoder configured to error correct the demodulated data; a FEC encoder configured to encode the error corrected demodulated data; an interleaver configured to interleave the FEC encoded data and output the interleaved FEC encoded data to the posteriori probability demodulator; and a symbol compressor/decompressor configured to compress symbol data from the a posteriori demodulator and store the compressed data in a symbol memory and configured to decompress compressed symbol data stored in the symbol memory.

Abstract: Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

Abstract: A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.

Abstract: A scalar/vector processor includes a plurality of functional units (252, 260, 262, 264, 266, 268, 270). At least one of the functional units includes a vector section (210) for operating on at least one vector and a scalar section (220) for operating on at least one scalar. The vector section and scalar section of the functional unit co-operate by the scalar section being arranged to provide and/or consume at least one scalar required by and/or supplied by the vector section of the functional unit.

Abstract: Various embodiments relate to a memory device in a turbo decoder and a related method for allocating data into the memory device. Different communications standards use data blocks of varying sizes when enacting block decoding of concatenated convolutional codes. The memory device efficiently minimizes space while enabling a higher throughput of the turbo decoder by enabling a plurality of memory banks of equal size. The number of memory banks may be limited by the amount of unused space in the memory banks, which may be a waste of area on an IC chip. Using the address associated with the maximum value of the data block, the memory may be split into a plurality of memory blocks according to the most-significant bits of the maximum address, with a number of parallel SISO decoders matching the number of memory banks. This may enable higher throughput while minimizing area on the IC chip.