Abstract: Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.

Abstract: Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.

Abstract: Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

Abstract: A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.

Abstract: Various embodiments relate to a memory device in a turbo decoder and a related method for allocating data into the memory device. Different communications standards use data blocks of varying sizes when enacting block decoding of concatenated convolutional codes. The memory device efficiently minimizes space while enabling a higher throughput of the turbo decoder by enabling a plurality of memory banks of equal size. The number of memory banks may be limited by the amount of unused space in the memory banks, which may be a waste of area on an IC chip. Using the address associated with the maximum value of the data block, the memory may be split into a plurality of memory blocks according to the most-significant bits of the maximum address, with a number of parallel SISO decoders matching the number of memory banks. This may enable higher throughput while minimizing area on the IC chip.

Abstract: A data processing system, a turbo decoding system, an address generator and a method of reconfiguring a turbo decoding method is provided. The data processing system (101) comprises the turbo decoding system (100). The turbo decoding system (100) comprises electronic circuits. The electronic circuits comprises: a memory (108), the address generator (102), and a Soft Input Soft Output decoder (106). The address generator (102) is operative to produce a sequence of addresses according to an interleaving scheme. The address generator can support multiple interleaving schemes. The address generator (102) is operative to receive reconfiguration information. The address generator (102) is operative to reconfigure during operational use the interleaving scheme in dependency on the reconfiguration information.

Abstract: A data processor (200) includes an operation execution unit (225) for executing instructions from an instruction memory (210) indicated by a program counter (220). A loop control circuit (230) stores respective associated loop information for a plurality of instruction loops in a register bank (232). The loop information includes at least an indication of an end of the loop and a loop count for indicating a number of times the loop should be executed. The loop control circuit (230) detects that one of the loops needs to be executed and in response to said detection, loads the loop information for the corresponding loop, and controls the program counter to execute the corresponding loop according to the loaded loop information. The loop information is initialized in response to a loop initialization instruction (240), where the initialization instruction is issued prior to and independent of a start of the loop initialized by the loop information.

Abstract: A scalar/vector processor includes a plurality of functional units (252, 260, 262, 264, 266, 268, 270). At least one of the functional units includes a vector section (210) for operating on at least one vector and a scalar section (220) for operating on at least one scalar. The vector section and scalar section of the functional unit co-operate by the scalar section being arranged to provide and/or consume at least one scalar required by and/or supplied by the vector section of the functional unit.