Patents by Inventor O-seob Jeon

O-seob Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9666512
    Abstract: A semiconductor package with a leadframe to mount a transistor device prevents malfunction. The semiconductor package includes a leadframe including at least one or more transistor die attach pads where a first transistor device and a second transistor device are arranged, a driver die attach pad where a driver semiconductor chip is arranged, a first driver lead electrically connected to the driver semiconductor chip, and a second driver lead arranged between the first driver lead and the at least one or more transistor die attach pads, a chip bonding wire electrically connecting the first transistor device with the driver semiconductor chip, a first transistor bonding wire electrically connecting the first driver lead with the second transistor device, and a first insulator arranged on the second driver lead to insulate the second driver lead and the first transistor bonding wire from each other.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: May 30, 2017
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Seung-won Im, O-seob Jeon, Joon-seo Son
  • Publication number: 20150332992
    Abstract: A semiconductor package with a leadframe to mount a transistor device prevents malfunction. The semiconductor package includes a leadframe including at least one or more transistor die attach pads where a first transistor device and a second transistor device are arranged, a driver die attach pad where a driver semiconductor chip is arranged, a first driver lead electrically connected to the driver semiconductor chip, and a second driver lead arranged between the first driver lead and the at least one or more transistor die attach pads, a chip bonding wire electrically connecting the first transistor device with the driver semiconductor chip, a first transistor bonding wire electrically connecting the first driver lead with the second transistor device, and a first insulator arranged on the second driver lead to insulate the second driver lead and the first transistor bonding wire from each other.
    Type: Application
    Filed: May 12, 2015
    Publication date: November 19, 2015
    Inventors: Seung-won IM, O-seob JEON, Joon-seo SON
  • Patent number: 9130065
    Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: September 8, 2015
    Assignee: Fairchild Korea Semiconductor, Ltd
    Inventors: Seungwon Im, O-Seob Jeon, Joon-seo Son, Keun-hyuk Lee, Yun-hwa Choi
  • Patent number: 8945992
    Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: February 3, 2015
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joon-seo Son, O-seob Jeon, Taek-keun Lee, Byoung-ok Lee
  • Publication number: 20140273349
    Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.
    Type: Application
    Filed: May 28, 2014
    Publication date: September 18, 2014
    Applicant: Fairchild Korea Semiconductor, Ltd.
    Inventors: Seung-won Lim, O-Seob Jeon, Joon-seo Son, Keun-hyuk Lee, Yun-hwa Choi
  • Publication number: 20140217572
    Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.
    Type: Application
    Filed: November 12, 2013
    Publication date: August 7, 2014
    Applicant: FAIRCHILD KOREA SEMICONDUCTOR, LTD.
    Inventors: Joo-Yang Eom, O-seob Jeon, Seung-Won Lim, Seung-Yong Choi
  • Patent number: 8766419
    Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: July 1, 2014
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Seung-won Lim, O-Seob Jeon, Joon-seo Son, Keun-kyuk Lee, Yun-hwa Choi
  • Patent number: 8723304
    Abstract: Provided is a semiconductor package having a power device and methods of fabricating the same. The semiconductor package includes a lead frame, a polymer layer component on the lead frame, a metal layer component on the polymer layer component, and a semiconductor chip on the metal layer component. The polymer layer component may include a material formed by adding alumina Al2O3, an aluminum nitride (AlN), or a boron nitride BN to an epoxy resin. The polymer layer component may have high thermal conductivity and good electric insulating characteristics.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: May 13, 2014
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: In-goo Kang, O-seob Jeon, Joon-seo Son
  • Patent number: 8604606
    Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: December 10, 2013
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joo-yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi
  • Publication number: 20130307145
    Abstract: A semiconductor package including a package substrate; a semiconductor chip on the package substrate; a first via contact on the package substrate; a second via contact on the semiconductor chip; a metal wiring, which is arranged on the first via contact and the second via contact and interconnects the first via contact and the second via contact; a first encapsulating material which is arranged between the metal wiring and the package substrate and encapsulates the semiconductor chip, the first via contact, and the second via contact; and a second encapsulating material which encapsulates the first encapsulating material and the metal wiring.
    Type: Application
    Filed: February 28, 2013
    Publication date: November 21, 2013
    Applicant: FAIRCHILD KOREA SEMICONDUCTOR LTD.
    Inventors: Yoon-jae CHUNG, Yong LIU, Seung-won IM, Byoung-ok LEE, Taek-keun LEE, Joon-seo SON, O-seob JEON
  • Publication number: 20120034741
    Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.
    Type: Application
    Filed: October 21, 2011
    Publication date: February 9, 2012
    Applicant: Fairchild Korea Semiconductor Co., Ltd.
    Inventors: Joon-seo Son, O-seob Jeon, Taek-keun Lee, Byoung-ok Lee
  • Patent number: 8067826
    Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: November 29, 2011
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Joon-Seo Son, O-seob Jeon, Taek-keun Lee, Byoung-ok Lee
  • Patent number: 7951645
    Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: May 31, 2011
    Assignee: Fairchild Korea Semiconductor, Ltd
    Inventors: Keun-hyuk Lee, O-seob Jeon, Seung-won Lim
  • Publication number: 20100289137
    Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.
    Type: Application
    Filed: July 28, 2010
    Publication date: November 18, 2010
    Applicant: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joo-yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi
  • Patent number: 7800224
    Abstract: A power device package according to the one embodiment of the present invention includes an insulating substrate with an interconnection pattern disposed on the insulating substrate. The interconnection pattern comprises a single conductive layer comprising a first metal layer, and a multiple conductive layer comprising another first metal layer and a second metal layer disposed on the another first metal layer. A plurality of wires are attached to an upper surface of the single conductive layer and/or an upper surface of the second metal layer of the multiple conductive layer. Contact pads on a power control semiconductor chip and a low power semiconductor chip driving the power control semiconductor chip are electrically connected to the wires.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: September 21, 2010
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joo-sang Lee, O-seob Jeon, Yong-suk Kwon, Frank Chen, Adams Zhu
  • Patent number: 7786570
    Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: August 31, 2010
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joo-Yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi
  • Publication number: 20100167470
    Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.
    Type: Application
    Filed: February 9, 2010
    Publication date: July 1, 2010
    Applicant: Fairchild Korea Semiconductor, Ltd.
    Inventors: Keun-hyuk Lee, O-seob Jeon, Seung-won Lim
  • Publication number: 20100155914
    Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 24, 2010
    Inventors: Seung-won Lim, O-Seob Jeon, Joon-seo Son, Keun-kyuk Lee, Yun-hwa Choi
  • Patent number: 7701048
    Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: April 20, 2010
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Keun-hyuk Lee, O-seob Jeon, Seung-won Lim
  • Patent number: 7687903
    Abstract: Provided are a power module including a power package and a control package that are provided separately and can be highly integrated, and method of fabricating the power module. The power module includes: a molded power package including at least one power device on a first lead frame; and a molded control package vertically stacked on the power package, and including at least one control device on a second lead frame. A first part of the first lead frame and a first part of the second lead frame are coupled to each other so that the power package and the control package can be electrically coupled to each other.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: March 30, 2010
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Joon-seo Son, Seung-won Lim, O-seob Jeon