Patents by Inventor O-seob Jeon

O-seob Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7675148
    Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: March 9, 2010
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Seung-won Lim, O-Seob Jeon, Joon-seo Son, Keun-hyuk Lee, Yun-hwa Choi
  • Publication number: 20090243079
    Abstract: Provided is a semiconductor device package including a substrate formed of a silicon (Si)-based material. The semiconductor device package includes a first substrate which comprises first and second principal planes which are opposite each other, and a substrate body layer disposed between the first and second principal planes, the substrate body layer being formed of a silicon (Si)-based material; and at least one first semiconductor device which is mounted on the first principal plane.
    Type: Application
    Filed: March 17, 2009
    Publication date: October 1, 2009
    Inventors: Seung-won Lim, O-seob Jeon, Seung-yong Choi, Joon-seo Son, Man-kyo Jong
  • Publication number: 20090194869
    Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.
    Type: Application
    Filed: January 23, 2009
    Publication date: August 6, 2009
    Applicant: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joo-yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi
  • Publication number: 20090194859
    Abstract: Provided is a semiconductor package having a power device and methods of fabricating the same. The semiconductor package includes a lead frame, a polymer layer component on the lead frame, a metal layer component on the polymer layer component, and a semiconductor chip on the metal layer component. The polymer layer component may include a material formed by adding alumina Al2O3 an aluminum nitride (AlN), or a boron nitride BN to an epoxy resin. The polymer layer component may have high thermal conductivity and good electric insulating characteristics.
    Type: Application
    Filed: January 23, 2009
    Publication date: August 6, 2009
    Applicant: Fairchild Korea Semiconductor, Ltd.
    Inventors: In-goo Kang, O-seob Jeon, Joon-seo Son
  • Publication number: 20090127681
    Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first die-pad on which a semiconductor chip is mounted on a bottom surface of the first die-pad, a support plate disposed adjacent to a lateral surface of the first die-pad, a support prop protruding from the support plate, and supporting the first die-pad, and a package body that encapsulates the first die-pad, the semiconductor chip, and the support plate.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 21, 2009
    Applicant: Fairchild Korea Semiconductor Ltd.
    Inventors: Joon-seo Son, Seung-won Lim, O-seob Jeon
  • Publication number: 20090129028
    Abstract: Provided are a power module including a power package and a control package that are provided separately and can be highly integrated, and method of fabricating the power module. The power module includes: a molded power package including at least one power device on a first lead frame; and a molded control package vertically stacked on the power package, and including at least one control device on a second lead frame. A first part of the first lead frame and a first part of the second lead frame are coupled to each other so that the power package and the control package can be electrically coupled to each other.
    Type: Application
    Filed: July 24, 2008
    Publication date: May 21, 2009
    Inventors: Joon-seo Son, Seung-won Lim, O-seob Jeon
  • Publication number: 20080224285
    Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 18, 2008
    Inventors: Seung-won Lim, O-Seob Jeon, Joon-seo Son, Keun-hyuk Lee, Yun-hwa Choi
  • Publication number: 20080164589
    Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.
    Type: Application
    Filed: January 8, 2008
    Publication date: July 10, 2008
    Applicant: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joon-seo Son, O-seob Jeon, Taek-keun Lee, Byoung-ok Lee
  • Publication number: 20080157310
    Abstract: A power device package according to the one embodiment of the present invention includes an insulating substrate with an interconnection pattern disposed on the insulating substrate. The interconnection pattern comprises a single conductive layer comprising a first metal layer, and a multiple conductive layer comprising another first metal layer and a second metal layer disposed on the another first metal layer. A plurality of wires are attached to an upper surface of the single conductive layer and/or an upper surface of the second metal layer of the multiple conductive layer. Contact pads on a power control semiconductor chip and a low power semiconductor chip driving the power control semiconductor chip are electrically connected to the wires.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 3, 2008
    Applicant: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joo-sang Lee, O-seob Jeon, Yong-suk Kwon, Frank Chen, Adams Zhu
  • Patent number: 7315077
    Abstract: Provided are a molded leadless package, and a sawing type molded leadless package and method of manufacturing same. The molded leadless package includes a lead frame pad having first and second surfaces opposite to each other. A semiconductor chip is adhered to the first surface of the lead frame pad. A lead is electrically coupled to the semiconductor chip. A molding material covers the lead frame pad, the semiconductor chip, and the lead and exposes a portion of the lead and a portion of the second surface of the lead frame pad. A step difference is formed between a surface of the molding material covering the second surface of the lead frame pad and the second surface of the lead frame pad itself. The sawing type molded leadless package includes a short-circuit preventing member that is post-shaped or convex, and protruding from the lower surface of the die pad.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: January 1, 2008
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Yoon-hwa Choi, Shi-baek Nam, O-seob Jeon, Rajeev Dinkar Joshi, Maria Cristina B. Estacio
  • Publication number: 20070257351
    Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.
    Type: Application
    Filed: May 3, 2007
    Publication date: November 8, 2007
    Applicant: Fairchild Korea Semiconductor, Ltd.
    Inventors: Keun-hyuk Lee, O-seob Jeon, Seung-won Lim
  • Publication number: 20070181984
    Abstract: A semiconductor package has a structure in which a leadframe pad to which a semiconductor die is attached and inner leads electrically connected to the leadframe pad are covered by a molded housing, and outer leads extending from the inner leads protrude from a side surface of the molded housing to the outside. The outer leads include a first outer lead disposed in a central portion of the molded housing, second and third outer leads respectively disposed in a right and left of the first outer lead. The second and third outer leads each have bent portions in portions where they are adjacent to the side surface of the molded housing, the bent portions protruding to increase a space between the first outer lead and the bent portions in the molded housing. At least one of the bent portions of the second and third outer leads is covered by an extended portion of the molded housing.
    Type: Application
    Filed: April 3, 2007
    Publication date: August 9, 2007
    Applicant: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joon-seo Son, Shi-baek Nam, O-seob Jeon
  • Patent number: 7208819
    Abstract: A power module package is provided. The power module package includes a power circuit element, a control circuit element, a lead frame, a heat sink, and an epoxy molding compound (EMC). The control circuit element is connected to the power circuit and controls chips in the power circuit. The lead frame has external connecting means formed at the edges thereof, and a down set part, namely, formed between the external connecting means. The lead frame has a first surface to which the power circuit and the control circuit are attached, and a second surface used as a heat dissipating path, in particular, the power circuit is attached to the down set part. The heat sink which is closely attached to the down set part of the second surface of the lead frame by an adhesive. The EMC surrounds the power circuit, the control circuit, the lead frame and the heat sink, and exposes the external connecting means of the lead frame and a side of the heat sink.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: April 24, 2007
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Gi-young Jeun, Sung-min Park, Joo-sang Lee, Sung-won Lim, O-seob Jeon, Byoung-ok Lee, Young-gil Kim, Gwi-gyeon Yang
  • Patent number: 7199461
    Abstract: A semiconductor package has a structure in which a leadframe pad to which a semiconductor die is attached and inner leads electrically connected to the leadframe pad are covered by a molded housing, and outer leads extending from the inner leads protrude from a side surface of the molded housing to the outside. The outer leads include a first outer lead disposed in a central portion of the molded housing, second and third outer leads respectively disposed in a right and left of the first outer lead. The second and third outer leads each have bent portions in portions where they are adjacent to the side surface of the molded housing, the bent portions protruding to increase a space between the first outer lead and the bent portions in the molded housing. At least one of the bent portions of the second and third outer leads is covered by an extended portion of the molded housing.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: April 3, 2007
    Assignee: Fairchild Korea Semiconductor, Ltd
    Inventors: Joon-seo Son, Shi-baek Nam, O-seob Jeon
  • Patent number: 7061080
    Abstract: A power module package is provided. The power module package includes a power circuit element, a control circuit element, a lead frame, a heat sink, and an epoxy molding compound (EMC). The control circuit element is connected to the power circuit and controls chips in the power circuit. The lead frame has external connecting means formed at the edges thereof, and a down set part, namely, formed between the external connecting means. The lead frame has a first surface to which the power circuit and the control circuit are attached, and a second surface used as a heat dissipating path, in particular, the power circuit is attached to the down set part. The heat sink which is closely attached to the down set part of the second surface of the lead frame by an adhesive. The EMC surrounds the power circuit, the control circuit, the lead frame and the heat sink, and exposes the external connecting means of the lead frame and a side of the heat sink.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: June 13, 2006
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Gi-young Jeun, Sung-min Park, Joo-sang Lee, Sung-won Lim, O-seob Jeon, Byoung-ok Lee, Young-gil Kim, Gwi-gyeon Yang
  • Publication number: 20050104168
    Abstract: Provided are a molded leadless package, and a sawing type molded leadless package and method of manufacturing same. The molded leadless package includes a lead frame pad having first and second surfaces opposite to each other. A semiconductor chip is adhered to the first surface of the lead frame pad. A lead is electrically coupled to the semiconductor chip. A molding material covers the lead frame pad, the semiconductor chip, and the lead and exposes a portion of the lead and a portion of the second surface of the lead frame pad. A step difference is formed between a surface of the molding material covering the second surface of the lead frame pad and the second surface of the lead frame pad itself. The sawing type molded leadless package includes a short-circuit preventing member that is post-shaped or convex, and protruding from the lower surface of the die pad.
    Type: Application
    Filed: November 12, 2004
    Publication date: May 19, 2005
    Inventors: Yoon-hwa Choi, Shi-baek Nam, O-seob Jeon, Rajeev Joshi, Maria Estacio
  • Publication number: 20050056918
    Abstract: A power module package is provided. The power module package includes a power circuit element, a control circuit element, a lead frame, a heat sink, and an epoxy molding compound (EMC). The control circuit element is connected to the power circuit and controls chips in the power circuit. The lead frame has external connecting means formed at the edges thereof, and a down set part, namely, formed between the external connecting means. The lead frame has a first surface to which the power circuit and the control circuit are attached, and a second surface used as a heat dissipating path, in particular, the power circuit is attached to the down set part. The heat sink which is closely attached to the down set part of the second surface of the lead frame by an adhesive. The EMC surrounds the power circuit, the control circuit, the lead frame and the heat sink, and exposes the external connecting means of the lead frame and a side of the heat sink.
    Type: Application
    Filed: October 26, 2004
    Publication date: March 17, 2005
    Applicant: Fairchild Korea Semiconductor Ltd.
    Inventors: Gi-young Jeun, Sung-min Park, Joo-sang Lee, Sung-won Lim, O-seob Jeon, Byoung-ok Lee, Young-gil Kim, Gwi-gyeon Yang
  • Publication number: 20040232541
    Abstract: A semiconductor package has a structure in which a leadframe pad to which a semiconductor die is attached and inner leads electrically connected to the leadframe pad are covered by a molded housing, and outer leads extending from the inner leads protrude from a side surface of the molded housing to the outside. The outer leads include a first outer lead disposed in a central portion of the molded housing, second and third outer leads respectively disposed in a right and left of the first outer lead. The second and third outer leads each have bent portions in portions where they are adjacent to the side surface of the molded housing, the bent portions protruding to increase a space between the first outer lead and the bent portions in the molded housing. At least one of the bent portions of the second and third outer leads is covered by an extended portion of the molded housing.
    Type: Application
    Filed: January 21, 2004
    Publication date: November 25, 2004
    Inventors: Joon-seo Son, Shi-baek Nam, O-seob Jeon
  • Patent number: 6774465
    Abstract: A semiconductor power module in which a power circuit chip and a control circuit chip are integrated in a package, is provided. The semiconductor power module includes a case; a terminal inserted into the case, the terminal including portions protruding upward to the outside of the case, and portions exposed in the case; a first substrate to which the power circuit chip is attached, the first substrate attached to the case for encapsulating the bottom of the package; a second substrate to which the control circuit chip is attached, the second substrate being spaced from the first substrate at a predetermined interval in a perpendicular direction in the case; and a cover for covering the top of the case, and for encapsulating the top of the package.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: August 10, 2004
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Keun hyuk Lee, Ji-hwan Kim, Dae-woong Chung, O-seob Jeon
  • Patent number: 6710439
    Abstract: A power semiconductor module in which a main circuit terminal lead frame part and a control circuit lead frame part are bent toward a main circuit lead frame part, is provided. The power semiconductor module includes a main circuit part; a control circuit part and a control circuit terminal which are placed along a plane perpendicular to the main circuit part; a main circuit terminal placed along another plane perpendicular to the main circuit part, facing the control circuit part the control circuit terminal; a bonding wire; and a mold compound. Accordingly, it is possible to realize a light and compact intelligent power module that is simple to manufactured at a low cost.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: March 23, 2004
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Keun-hyuk Lee, Gi-Young Jeun, O-seob Jeon