Patents by Inventor Oded Lempel
Oded Lempel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11258887Abstract: In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.Type: GrantFiled: June 23, 2020Date of Patent: February 22, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ilan Pardo, Mark B. Rosenbluth, Idan Burstein, Rui Xu, Oded Lempel, Tsofia Eshel
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Publication number: 20210400124Abstract: In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.Type: ApplicationFiled: June 23, 2020Publication date: December 23, 2021Inventors: Ilan Pardo, Mark B. Rosenbluth, Idan Burstein, Rui Xu, Oded Lempel, Tsofia Eshel
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Patent number: 9448879Abstract: An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.Type: GrantFiled: December 22, 2011Date of Patent: September 20, 2016Assignee: INTEL CORPORATIONInventors: Theodros Yigzaw, Oded Lempel, Hisham Shafi, Geeyarpuram N. Santhanakrishnan, Jose A. Vargas, Ganapati N Srinivasa, Mohan J Kumar, Larisa Novakovsky, Lihu Rappoport, Chen Koren, Julius Mandelblat, Michael Mishaeli
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Publication number: 20140298140Abstract: An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.Type: ApplicationFiled: December 22, 2011Publication date: October 2, 2014Inventors: Theodros Yigzaw, Oded Lempel, Hisham Hafi, Geeyarpuram N Santhanakrisnan, Jose A Vargas, Ganapati N Srinivasa, Mohan J Kumar, Larisa Novakovsky, Lihu Rappoport, Chen Koren, Julius Yuli Mandelblat
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Patent number: 8782374Abstract: Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss.Type: GrantFiled: December 2, 2008Date of Patent: July 15, 2014Assignee: Intel CorporationInventors: Lihu Rappoport, Chen Koren, Franck Sala, Oded Lempel, Ido Ouziel, Ron Gabor, Gregory Pribush, Lior Libis
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Patent number: 8433850Abstract: Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.Type: GrantFiled: December 2, 2008Date of Patent: April 30, 2013Assignee: Intel CorporationInventors: Lihu Rappoport, Chen Koren, Franck Sala, Ilhyun Kim, Lior Libis, Ron Gabor, Oded Lempel
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Patent number: 8127085Abstract: Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.Type: GrantFiled: December 31, 2008Date of Patent: February 28, 2012Assignee: Intel CorporationInventors: Lihu Rappoport, Chen Koren, Franck Sala, Oded Lempel, Ido Ouziel, Ilhyun Kim, Ron Gabor, Lior Libis, Gregory Pribush
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Publication number: 20100138610Abstract: Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss.Type: ApplicationFiled: December 2, 2008Publication date: June 3, 2010Inventors: Lihu Rappoport, Chen Koren, Franck Sala, Oded Lempel, Ido Ouziel, Ron Gabor, Gregory Pribush, Lior Libis
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Publication number: 20100138608Abstract: Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.Type: ApplicationFiled: December 31, 2008Publication date: June 3, 2010Inventors: Lihu Rappoport, Chen Koren, Franck Sala, Oded Lempel, Ido Ouziel, Ilhyun Kim, Ron Gabor, Lior Libis, Gregory Pribush
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Publication number: 20100138611Abstract: Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.Type: ApplicationFiled: December 2, 2008Publication date: June 3, 2010Inventors: LIHU RAPPOPORT, Chen Koren, Franck Sala, Ilhyun Kim, Lior Libis, Ron Gabor, Oded Lempel
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Patent number: 7290179Abstract: Embodiments of the present invention relate to detecting and clearing a soft error in a cache.Type: GrantFiled: December 1, 2003Date of Patent: October 30, 2007Assignee: Intel CorporationInventors: Oded Lempel, Ittai Anati, Zeev Offen
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Patent number: 7174444Abstract: A system and method of early branch prediction in a processor to evaluate, typically before a full branch prediction is made, ways in a branch target buffer to determine if any of said ways corresponds to a valid unconditional branch, and upon such determination, to generate a signal to prevent a read of a next sequential chunk.Type: GrantFiled: March 31, 2003Date of Patent: February 6, 2007Assignee: Intel CorporationInventors: Eran Altshuler, Oded Lempel, Robert Valentine, Nicolas Kacevas
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Publication number: 20060036834Abstract: A trace management architecture to enable the reuse of uops within one or more repeated traces. More particularly, embodiments of the invention relate to a technique to prevent multiple accesses to various functional units within a trace management architecture by reusing traces or sequences of traces that are repeated during a period of operation of the microprocessor, avoiding performance gaps due to multiple trace cache accesses and increasing the rate at which uops can be executed within a processor.Type: ApplicationFiled: August 13, 2004Publication date: February 16, 2006Inventors: Subramaniam Maiyuran, Peter Smith, Varghese George, Eran Altshuler, Robert Valentine, Zeev Offen, Oded Lempel
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Publication number: 20050262332Abstract: A system and method for predicting a branch target for a current instruction in a microprocessor, the system comprising a cache storing indirect branch instructions and a path register. The path register is updated on certain branches by an XOR operation on the path register and the branch instruction, followed by the addition of one or more bits to the register. The cache is indexed by performing an operation on a portion of the current instruction address and the path register; the entry returned, if any, may be used to predict the target of the current instruction.Type: ApplicationFiled: March 31, 2003Publication date: November 24, 2005Inventors: Lihu Rappoport, Ronny Ronen, Nicolas Kacevas, Oded Lempel
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Publication number: 20050149781Abstract: Embodiments of the present invention relate to detecting and clearing a soft error in a cache.Type: ApplicationFiled: December 1, 2003Publication date: July 7, 2005Inventors: Oded Lempel, Ittai Anati, Zeev Offen
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Publication number: 20050027974Abstract: Embodiments of the present invention provide a method, apparatus and system for conserving resources such as power resources in processor instruction pipelines. A branch prediction unit may predict whether a branch is to be taken and an instruction fetch unit may fetch a next sequential instruction. A control circuit may be coupled to the branch prediction unit. The control circuit may abort the next sequential instruction if the branch is predicted to be taken.Type: ApplicationFiled: July 31, 2003Publication date: February 3, 2005Inventor: Oded Lempel
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Publication number: 20040193843Abstract: A system and method of early branch prediction in a processor to evaluate, typically before a full branch prediction is made, ways in a branch target buffer to determine if any of said ways corresponds to a valid unconditional branch, and upon such determination, to generate a signal to prevent a read of a next sequential chunk.Type: ApplicationFiled: March 31, 2003Publication date: September 30, 2004Inventors: Eran Altshuler, Oded Lempel, Robert Valentine, Nicolas Kacevas
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Patent number: 6646647Abstract: Embodiments of the present invention relate to displaying images from memory. A plurality of pixel attributes are retrieved from memory in a single memory transaction. At least one attribute corresponds to one scan line of a display and another attribute corresponds to another scan line of the display. A portion of one scan line using the corresponding pixel attribute is displayed. The pixel attributes corresponding to another scan line is stored in a buffer.Type: GrantFiled: September 29, 2000Date of Patent: November 11, 2003Assignee: Intel CorporationInventors: Roman Surgutchik, Gad S Shaeffer, Oded Lempel, Robert Valentine
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Patent number: 6647545Abstract: A processor includes a host interface unit capable of generating at least one branch trace message (BTM), the host interface unit is coupled to a memory so as to store the at least one BTM in the memory and the processor is embodied on an integrated circuit (IC).Type: GrantFiled: February 14, 2000Date of Patent: November 11, 2003Assignee: Intel CorporationInventors: Tsvika Kurts, Roman Surgutchik, Oded Lempel, Ittai Anati, Haim Lustig
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Patent number: 6601161Abstract: A system and method for predicting a branch target for a current instruction in a microprocessor, the system comprising a cache storing indirect branch instructions and a path register. The path register is updated on certain branches by an XOR operation on the path register and the branch instruction, followed by the addition of one or more bits to the register. The cache is indexed by performing an operation on a portion of the current instruction address and the path register; the entry returned, if any, may be used to predict the target of the current instruction.Type: GrantFiled: December 30, 1998Date of Patent: July 29, 2003Assignee: Intel CorporationInventors: Lihu Rappoport, Ronny Ronen, Nicolas Kacevas, Oded Lempel