Abstract: A system and method for predicting a branch target for a current instruction in a microprocessor, the system comprising a cache storing indirect branch instructions and a path register. The path register is updated on certain branches by an XOR operation on the path register and the branch instruction, followed by the addition of one or more bits to the register. The cache is indexed by performing an operation on a portion of the current instruction address and the path register; the entry returned, if any, may be used to predict the target of the current instruction.

Abstract: A method and apparatus for preventing over-prefetching from a buffer receives an address of a last data set item in a data buffer, and reads data from the data buffer into a read streamer buffer starting at a data buffer start address until the address of said last item.

Abstract: A method and apparatus for fast unsigned integral division, utilized in compositing images, sounds or other data, is provided. Compositing utilizes a division step. The divisor is the value of two to the Nth power minus one. The division comprises the steps of making a copy of the first number, thus producing a third number. The first number is shifted to the right by N. The third number is biased, and is then added to the first number. The resultant number is shifted right by N. This process results in a division by 2.sup.N -1, with short latency instructions, instead of the long latency instructions usually used for division operations.

Abstract: An apparatus includes a data array, control logic, an entry candidate table, and a future target table. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The entry candidate table is coupled to the control logic and is adapted to store offset information related to the position of a selected instruction within the trace segment. The future target table is coupled to the control logic and adapted to store a potential entry point into the trace segment. A method for caching instructions includes storing a first plurality of instructions in a first trace segment. A control flow instruction is identified from the first plurality of instructions and the outcome of the control flow instruction is predicted. The control flow instruction has a predicted taken target address and a predicted not-taken target address corresponding to the outcome predicted. The predicted not-taken target address is stored.

Abstract: An apparatus includes a data array and control logic. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The control logic allows the instructions of the trace segment to be sequentially retrieved beginning with a selected instruction. The selected instruction is offset from the first instruction of the trace segment. A method for caching instructions includes storing a first plurality of instructions in a first trace segment. A selected instruction of the first plurality of instructions is identified within the first trace segment. The selected instruction is offset from the first instruction of the first trace segment. The offset information related to the position of the selected instruction within the first trace segment is stored.

Abstract: A branch prediction unit includes a first branch target buffer, a second branch target buffer, and a static predictor. The first branch target buffer is adapted for storing a first plurality of branch history entries. The second branch target buffer is adapted for storing a second plurality of branch history entries. The static predictor is adapted for determining a static branch prediction for an encountered branch instruction. The second branch target buffer is further adapted to allocate a branch history entry based on the static prediction. A method for predicting program branches in a microprocessor includes fetching a program instruction to be executed by the microprocessor. It is determined if an entry corresponding to the program instruction is stored in a first branch target buffer, and if an entry corresponding to the program instruction is stored in a second branch target buffer. It is determined if the program instruction is a branch instruction.