Abstract: A method for manufacturing a capacitor electrode structure, according to which the following steps are executed: A substrate is provided, which comprises contact pads arranged in lines and rows on a surface of the substrate. The lines are non-parallel to the rows. A first mold is applied on the substrate. At least one first trench is formed into the first mold above the contact pads. The first trench spans over at least two contact pads arranged in one row. A first dielectric layer is applied on side walls of the at least one first trench for forming first supporting walls. A second mold is applied on the substrate. At least one second trench is formed into the second mold above the contact pads. The second trench spans over at least two contact pads arranged in one line. A second dielectric layer is applied on side walls of the at least one second trench for forming second supporting walls.

Abstract: A microscopic hole is produced in a dielectric layer having a dielectric first material, a first surface and a second surface. In one embodiment, the tapered through-hole is etched from the second surface of the layer to the first surface of the layer. The tapered hole provides a first cross section near the first surface of the dielectric layer and a second cross section near the second surface of dielectric layer. A cladding is deposited at the inner surface of the through-hole. The cladding includes a second material and provides a thickness decreasing from the second surface to the first surface.

Abstract: A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.

Abstract: An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements.

Abstract: A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42) of the masking layer (40) to the contact plugs (26). A conductive layer (50) covers the side walls (49) of the trenches (48) and the contact plugs (26) in order to form a first electrode (60) of a stacked capacitor (12). In an upper region (63), which is remote from the contact stack (26), the conductive layer (50) is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.

Abstract: A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.

Abstract: A method for manufacturing a capacitor electrode structure, according to which the following steps are executed: A substrate is provided, which comprises contact pads arranged in lines and rows on a surface of the substrate. The lines are non-parallel to the rows. A first mold is applied on the substrate. At least one first trench is formed into the first mold above the contact pads. The first trench spans over at least two contact pads arranged in one row. A first dielectric layer is applied on side walls of the at least one first trench for forming first supporting walls. A second mold is applied on the substrate. At least one second trench is formed into the second mold above the contact pads. The second trench spans over at least two contact pads arranged in one line. A second dielectric layer is applied on side walls of the at least one second trench for forming second supporting walls.

Abstract: A method for forming a capacitor structure, according to which the following consecutive steps are executed: providing a substrate having on its surface contact pads and a dielectric mold provided with at least one trench leaving exposed the contact pads; forming a first conductive layer on side walls of the trench in a top region of the trench the conductive layer being without contact to the contact pads; depositing a first dielectric layer; depositing a second conductive layer on the contact pad and on the side walls of the trench; depositing a second dielectric layer; depositing a third conductive layer; and forming a vertical plug interconnecting the first conductive layer and the third conductive layer.

Abstract: A method for forming an integrated circuit having openings in a mold layer and for producing capacitors is disclosed. In one embodiment, nanotubes or nanowires are grown vertically on a horizontal substrate surface. The nanotubes or nanowires serve as a template for forming openings in a mold layer. The substrate is covered with a mold material after the formation of the nanowires or nanotubes. One embodiment provides mold layers having openings with a much higher aspect ratio.

Abstract: A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.

Abstract: A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42) of the masking layer (40) to the contact plugs (26). A conductive layer (50) covers the side walls (49) of the trenches (48) and the contact plugs (26) in order to form a first electrode (60) of a stacked capacitor (12). In an upper region (63), which is remote from the contact stack (26), the conductive layer (50) is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.

Abstract: A method for fabricating patterned resist masks. Firstly, a photoresist film is applied on a semiconductor substrate in a customary manner, which photoresist film is then exposed by means of customary techniques. In the development step, a rinsing medium containing a cationic surfactant is used. If the patterned resist is dried after development, the sidewalls of the resist webs are rendered hydrophobic by the cationic surfactant, so that the contact angle can be increased to values of approximately 90°, reducing capillary forces acting on the webs of the patterned resist to approximately zero. As a result, even in the case of single-layer resist films, the line width of the webs can be reduced without a line collapse being observed.