Abstract: Aspects of the disclosure provide a method for video frame rotation. The method includes receiving a first tile from among a plurality of tiles forming a video frame. The first tile includes a first plurality of macro pixels where each macro pixel interleaves at least one pair of neighboring pixels in a first orientation. Further, the method includes de-interleaving the first plurality of macro pixels into first pixels, mapping the first pixels into first rotated neighboring pixels in a second orientation, and interleaving the first rotated neighboring pixels into first rotated macro pixels forming a first rotated tile.

Abstract: A method for operating a host device includes comparing a predetermined response of a peripheral device to a response token received from the peripheral device. The predetermined response and the response token are generated based on a first command transmitted from the host device to the peripheral device. The method further includes controlling a transfer of first data from a first memory to a peripheral control module based on the comparison between the predetermined response and the response token without interrupting a host control module, and selectively passing interrupts to the host control module when the predetermined response does not match the response token.

Abstract: To save power, a controller formats data packets for transmission to a remote device and then enters a low power mode. A direct memory access unit reads the formatted data packets and presents them to a communication interface for transmission to the remote device. A hardware logic unit matches acknowledgement and no-acknowledgement responses from the remote device for directing further packet transmission. When the hardware logic unit cannot match a response from the remote device it signals the controller to wake up for further processing.

Abstract: A host device includes a peripheral control module that includes a first memory register that receives data from a first memory and a direct memory access (DMA) module that communicates with the first memory. The host device also includes a host control module that receives data from the first memory. The host device also includes a DMA control module that communicates with the first memory register, the host control module and a second memory that includes a first memory array. The DMA control module compares contents of the first memory array to contents of the memory register and controls transfers of data from the first memory to the peripheral control module based on the comparison.

Abstract: A system includes first memory for storing data and a processing core for executing software instructions on the data that is received from the first memory. The system also includes a peripheral device configured to communicate with the processing core through a peripheral control module. The peripheral control module, also referred to as a peripheral control device, includes second memory. The peripheral control module also includes a comparator for governing data transfer transactions, without interrupting the processing core, based on a comparison. The comparator therefore compares expected responses to command sequences and received responses to the command sequences. The command sequences and responses to command sequences are associated with data packets to be exchanged between the first memory and the peripheral device.

Abstract: Embodiments of the present disclosure provide a method comprising providing 2-D or 3-D graphics content to a graphics processing module; processing the graphics content to generate a stream of images (e.g., three dimensional images and/or two dimensional images) for display, the stream having a frame rate; and governing a rate of processing the graphics content to limit the frame rate of the generated stream of images to be less than or equal to a frame rate threshold. Other embodiments may also be described and claimed.

Abstract: A host device includes a peripheral control module that includes a first memory register that receives data from a first memory and a direct memory access (DMA) module that communicates with the first memory. The host device also includes a host control module that receives data from the first memory. The host device also includes a DMA control module that communicates with the first memory register, the host control module and a second memory that includes a first memory array. The DMA control module compares contents of the first memory array to contents of the memory register and controls transfers of data from the first memory to the peripheral control module based on the comparison.

Abstract: To save power, a controller formats data packets for transmission to a remote device and then enters a low power mode. A direct memory access unit reads the formatted data packets and presents them to a communication interface for transmission to the remote device. A hardware logic unit matches acknowledgement and no-acknowledgement responses from the remote device for directing further packet transmission. When the hardware logic unit cannot match a response from the remote device it signals the controller to wake up for further processing.

Abstract: A host device includes a peripheral control module that includes a first memory register that receives data from a first memory and a direct memory access (DMA) module that communicates with the first memory. The host device also includes a host control module that receives data from the first memory. The host device also includes a DMA control module that communicates with the first memory register, the host control module and a second memory that includes a first memory array. The DMA control module compares contents of the first memory array to contents of the memory register and controls transfers of data from the first memory to the peripheral control module based on the comparison.