Abstract: A system includes an obsolete cache-line vector having a plurality of memory elements, wherein each memory element has a one-to-one correspondence to a cache line entry of a cache memory. The vector can capture cache line errors that occur at different times from an error detection logic associated with the cache memory. A counter can be coupled to the obsolete cache-line vector for tracking how many of the memory elements in the vector are activated. When a predetermined threshold is reached, a threshold comparator can release a trigger for further analysis. An error events logger can be used to track all of the errors that occurred. The error events logger can also use a time stamp, which can assist the RAS system in analyzing a correlation between the errors, such as patterns that occur and time differences between the errors.

Abstract: An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

Abstract: A circuit is presented which includes a first amplifier having an input, a transmission line having first and second ends. The first end of the transmission line is coupled to an input of the first amplifier and a plurality of channels. Each channel includes a plurality of resonators arranged to read out a plurality of qubits, respectively and a readout line arranged to receive read out signals from the plurality of resonators. The readout line of each channel is coupled to the transmission line and each channel is configured to output a respective signal in a respective frequency band which is different from frequency bands of other channels in the plurality of channels.

Abstract: A packet processing technique can include receiving a packet, and parsing the packet based on a protocol field to generate a parse result vector. The parse result vector is used to select between forwarding the packet to a virtual machine executing on a host processing integrated circuit, forwarding the packet to a physical media access controller, multicasting the packet to multiple virtual machines executing on the host processing integrated circuit, and sending the packet to a hypervisor.

Abstract: A system captures errors and stores an obsolete line bit qualifier per cache entry that can be used to dynamically mark a specific cache entry as obsolete. For example, the cache entry can be marked as obsolete after detecting repetitive single-bit errors on a same cache entry within a predetermined period of time. For cache lines marked as obsolete, a cache controller can ensure that the cache line entry remains unused. The detection of a repetitive single-bit error can be accomplished by implementing a counter per cache entry and a timer. The counter counts errors within a timer window, and a repetitive error is reported if the counter reaches a threshold level. By catching repetitive single-bit errors before such errors spread to multi-bit errors, the system can increase the life span of the server computer.

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

Abstract: Techniques are disclosed for transferring a message between a sender agent and a receiver agent via a shared memory having a main memory and a cache. Feedback data indicative of a number of read messages in the shared memory is generated by the receiver agent. The feedback data is sent from the receiver agent to the sender agent. A number of unread messages in the shared memory is estimated by the sender agent based on the number of read messages. A threshold for implementing a caching policy is set by the sender agent based on the feedback data. The message is designated as cacheable if the number of unread messages is less than the threshold and as non-cacheable if the number of unread messages is greater than the threshold. The message is written to the shared memory based on the designation.

Abstract: A packet processing technique can include receiving a packet, and parsing the packet based on a protocol field to generate a parse result vector. The parse result vector is used to select between forwarding the packet to a virtual machine executing on a host processing integrated circuit, forwarding the packet to a physical media access controller, multicasting the packet to multiple virtual machines executing on the host processing integrated circuit, and sending the packet to a hypervisor.

Abstract: Techniques to prioritize serially transmitted data are described. The sequence of serial data segments being transmitted across a communication interface is modified such that prioritized segments that may require a higher refresh rate are transmitted more frequently than regular data segments. A prioritization configuration register can be implemented in both the transmitter and the receiver such that both sides are programmed with the altered sequence of transmission. The prioritization configuration stored in the prioritization configuration register can indicate the points in the sequence where the out-of-order transmission occurs, and which data segments are transmitted in them. The transmitter can use this information to serialize the data segments according to the prioritization, and the receiver can re-parallelize the received data as indicated by the altered sequence.

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

Abstract: The technology relates to quantum computing devices and test arrangements for detecting information from the qubits of such devices. According to aspects of the technology, a Purcell filter is structured in a multi-pole architecture to provide a sharper filter response having a flatter signal pass band, sharper turn-off skirt, and enhanced out of band rejection. The system is able to determine the states of the qubits by detecting the frequency of the readout resonators of the test arrangement. The Purcell filter is configured to be sharply tuned to enable faster readout to avoid issues associated with a longer relaxation time (T1) of the qubits.

Abstract: A Josephson parametric device is presented, which includes an input port, an output port, and a signal path between the input port and the output port. The signal path includes a first section coupled to the input port and having a first passband, a second section coupled to the output port and having a second passband and a Josephson junction coupling element for parametric coupling between the first and second section. The Josephson junction coupling element is coupled to and interposed between the first section and the second section. The Josephson junction coupling element is configured such that, in response to the input port receiving a first signal at a first frequency lying within the first passband and the Josephson junction coupling element receiving a pump tone, the Josephson junction coupling element converts the first signal into a second signal with a second frequency lying within the second passband.

Abstract: A packet processing technique can include receiving a packet, and parsing the packet based on a protocol field to generate a parse result vector. The parse result vector is used to select between forwarding the packet to a virtual machine executing on a host processing integrated circuit, forwarding the packet to a physical media access controller, multicasting the packet to multiple virtual machines executing on the host processing integrated circuit, and sending the packet to a hypervisor.

Abstract: A circuit is presented which includes a first amplifier having an input, a transmission line having first and second ends. The first end of the transmission line is coupled to an input of the first amplifier and a plurality of channels. Each channel includes a plurality of resonators arranged to read out a plurality of qubits, respectively and a readout line arranged to receive read out signals from the plurality of resonators. The readout line of each channel is coupled to the transmission line and each channel is configured to output a respective signal in a respective frequency band which is different from frequency bands of other channels in the plurality of channels.

Abstract: A packet processing technique can include selecting a protocol field from the packet, and performing a comparison of the selected protocol field with comparison data in a compare logic array to output a protocol index. The protocol index can be used as an address to read parsing commands from a parse control table, and a parse result can be generated based on executing the parsing commands on the packet. The parse results are used to derive a parse result vector, which can be used by a forwarding engine to forward the packet.

Abstract: In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.

Abstract: Techniques are disclosed for transferring a message between a sender agent and a receiver agent via a shared memory having a main memory and a cache. Feedback data indicative of a number of read messages in the shared memory is generated by the receiver agent. The feedback data is sent from the receiver agent to the sender agent. A number of unread messages in the shared memory is estimated by the sender agent based on the number of read messages. A threshold for implementing a caching policy is set by the sender agent based on the feedback data. The message is designated as cacheable if the number of unread messages is less than the threshold and as non-cacheable if the number of unread messages is greater than the threshold. The message is written to the shared memory based on the designation.

Abstract: An apparatus includes a directional coupler and an absorptive low pass filter, in which the directional coupler has a first transmission line extending from a first port to a second port and a second transmission line extending from a third port to a fourth port, the first transmission line and the second transmission line configured such that a portion of a signal travelling from the first port onto the first transmission line is coupled to the second transmission line and towards the third port. The second port is connected to the fourth port of the directional coupler via the absorptive low pass filter. When the signal is input into the first port of the directional coupler and output through the third port of the directional coupler, the signal is substantially unattenuated if the frequency of the signal is in a passband of the absorptive low pass filter.

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

Abstract: One example includes a memory cell system. The memory cell system includes a quantizing loop configured to conduct a quantizing current in a first direction corresponding to storage of a first state of a stored memory state of the memory cell system and to conduct the quantizing current in a second direction opposite the first direction corresponding to storage of a second state of the stored memory state of the memory cell system. The memory cell system also includes a bias element arranged in the quantizing loop and which is configured to provide a substantially constant flux bias of the quantizing loop in each of the first and second states of the stored memory state.