Abstract: An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

Abstract: A packet processing technique can include selecting a protocol field from the packet, and performing a comparison of the selected protocol field with comparison data in a compare logic array to output a protocol index. The protocol index can be used as an address to read parsing commands from a parse control table, and a parse result can be generated based on executing the parsing commands on the packet. The parse results are used to derive a parse result vector, which can be used by a forwarding engine to forward the packet.

Abstract: One example includes a memory cell system. The memory cell system includes a quantizing loop configured to conduct a quantizing current in a first direction corresponding to storage of a first state of a stored memory state of the memory cell system and to conduct the quantizing current in a second direction opposite the first direction corresponding to storage of a second state of the stored memory state of the memory cell system. The memory cell system also includes a bias element arranged in the quantizing loop and which is configured to provide a substantially constant flux bias of the quantizing loop in each of the first and second states of the stored memory state.

Abstract: In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.

Abstract: A system, comprising: a configurable parser that comprises one or more configurable parsing engines, wherein the configurable parser is arranged to receive a packet and to extract from the packet headers associated with a set of protocols that comprises at least one protocol; a packet type detection unit that is arranged to determine a type of the packet in response to the set of protocols; and a configurable data integrity unit that comprises a configuration unit and at least one configurable data integrity engine; wherein the configuration unit is arranged to configure the at least one configurable data integrity engine according to the set of protocols; and wherein the at least one configurable data integrity engine is arranged to perform data integrity processing of the packet to provide at least one data integrity result.

Abstract: Interactive compilation of software to a hardware language may be performed to satisfy formal verification constraints. Source code for software to be executed on a hardware design may be received. Intermediate code may be generated from the source code as part of translating the source code to a hardware language used to specify the hardware design. The intermediate code may be provided via an interface and updates to the intermediate code may be received. The updated source code may then be used to complete translation of the source code to the hardware language.

Abstract: One example includes a memory cell system that includes a quantizing loop that conducts a quantizing current in a first direction corresponding to a first stored memory state and to conduct the quantizing current in a second direction corresponding to a second stored memory state. The system also includes a bias element configured to provide a substantially constant flux bias of the quantizing loop in each of the first and second states of the stored memory state. The stored memory state can be read from the memory cell system in response to the substantially constant flux bias and a read current that is provided to the memory cell system. The system further includes a tunable energy element that is responsive to a write current that is provided to the memory cell system to change the state of the stored memory state between the first state and the second state.

Abstract: Examples described in this disclosure relate to a memory cell with Josephson phase-based torque. In one example, a memory cell including a first inductor and a magnetic Josephson junction (MJJ) coupled to the first inductor to form a loop is provided. The MJJ may include a free magnetic layer formed above a non-magnetic layer, and a fixed magnetic layer below the non-magnetic layer. A first state of the memory cell corresponds to a first magnetization of the free magnetic layer that is parallel to a magnetization of the fixed magnetic layer and the second state of the memory cell corresponds to a second magnetization of the free magnetic layer that is anti-parallel to the magnetization of the fixed magnetic layer. The memory cell is configured to switch from the first state to the second state based on whether the MJJ is in a zero-state or a ?-state.

Abstract: One example includes a superconducting bidirectional current driver. The current driver includes a first direction superconducting latch that is activated in response to a first activation signal to provide a first current path of an input current through a bidirectional current load in a first direction. The current driver also includes a second direction superconducting latch that is activated in response to a second activation signal to provide a second current path of the input current through the bidirectional current load in a second direction opposite the first direction.

Abstract: One example includes a memory cell system that includes a quantizing loop that conducts a quantizing current in a first direction corresponding to a first stored memory state and to conduct the quantizing current in a second direction corresponding to a second stored memory state. The system also includes a bias element configured to provide a substantially constant flux bias of the quantizing loop in each of the first and second states of the stored memory state. The stored memory state can be read from the memory cell system in response to the substantially constant flux bias and a read current that is provided to the memory cell system. The system further includes a tunable energy element that is responsive to a write current that is provided to the memory cell system to change the state of the stored memory state between the first state and the second state.

Abstract: Examples described in this disclosure relate to a memory cell with Josephson phase-based torque. In one example, a memory cell including a first inductor and a magnetic Josephson junction (MJJ) coupled to the first inductor to form a loop is provided. The MJJ may include a free magnetic layer formed above a non-magnetic layer, and a fixed magnetic layer below the non-magnetic layer. A first state of the memory cell corresponds to a first magnetization of the free magnetic layer that is parallel to a magnetization of the fixed magnetic layer and the second state of the memory cell corresponds to a second magnetization of the free magnetic layer that is anti-parallel to the magnetization of the fixed magnetic layer. The memory cell is configured to switch from the first state to the second state based on whether the MJJ is in a zero-state or a ?-state.

Abstract: Real-time reconfigurability of quantum object connectivity can be provided with one or more quantum routers that can each be configured as either or both of a single-pole double-throw switch and a cross-point switch. The quantum router includes variable-inductance coupling elements in RF-SQUIDs having inductors transformer-coupled to two control flux lines, one providing a static current and the other providing a dynamic current, the direction of which can be toggled to couple or uncouple quantum objects, such as qubits, based on the dynamic current direction to provide reconfigurable quantum routing.

Abstract: Real-time reconfigurability of quantum object connectivity can be provided with one or more quantum routers that can each be configured as either or both of a single-pole double-throw switch and a cross-point switch. The quantum router includes variable-inductance coupling elements in RF-SQUIDs having inductors transformer-coupled to two control flux lines, one providing a static current and the other providing a dynamic current, the direction of which can be toggled to couple or uncouple quantum objects, such as qubits, based on the dynamic current direction to provide reconfigurable quantum routing.

Abstract: A system, comprising: a configurable parser that comprises one or more configurable parsing engines, wherein the configurable parser is arranged to receive a packet and to extract from the packet headers associated with a set of protocols that comprises at least one protocol; a packet type detection unit that is arranged to determine a type of the packet in response to the set of protocols; and a configurable data integrity unit that comprises a configuration unit and at least one configurable data integrity engine; wherein the configuration unit is arranged to configure the at least one configurable data integrity engine according to the set of protocols; and wherein the at least one configurable data integrity engine is arranged to perform data integrity processing of the packet to provide at least one data integrity result

Abstract: One example includes a parametric amplifier system. The system includes an input/output (I/O) transmission line to propagate a signal tone. The system also includes a non-linearity circuit comprising at least one Josephson junction to provide at least one inductive path of the signal tone in parallel with the at least one Josephson junction. The system further includes an impedance matching network coupled to the I/O transmission line to provide impedance matching of the tone signal between the I/O transmission line and the non-linearity element.

Abstract: One embodiment describes a Josephson transmission line (JTL) system. The system includes a plurality of JTL stages that are arranged in series. The system also includes a clock transformer comprising a primary inductor configured to propagate an AC clock signal and a secondary inductor arranged in a series loop with at least two of the plurality of JTL stages. The clock transformer can be configured to propagate a single flux quantum (SFQ) pulse to set a respective one of the plurality of JTL stages in response to a first phase of the AC clock signal and to reset the respective one of the plurality of JTL stages in response to a second phase of the AC clock signal that is opposite the first phase.

Abstract: A tunable bus-mediated coupling system is provided that includes a first input port coupled to a first end of a variable inductance coupling element through a first resonator and a second input port coupled to a second end of the variable inductance coupling element through a second resonator. The first input port is configured to be coupled to a first qubit, and the second output port is configured to be coupled to a second qubit. A controller is configured to control the inductance of the variable inductance coupling element between a low inductance state to provide strong coupling between the first qubit and the second qubit and a high inductance state to provide isolation between the first qubit and the second qubit.

Abstract: A system, comprising: a configurable parser that comprises one or more configurable parsing engines, wherein the configurable parser is arranged to receive a packet and to extract from the packet headers associated with a set of protocols that comprises at least one protocol; a packet type detection unit that is arranged to determine a type of the packet in response to the set of protocols; and a configurable data integrity unit that comprises a configuration unit and at least one configurable data integrity engine; wherein the configuration unit is arranged to configure the at least one configurable data integrity engine according to the set of protocols; and wherein the at least one configurable data integrity engine is arranged to perform data integrity processing of the packet to provide at least one data integrity result.

Abstract: One example includes a parametric amplifier system. The system includes an input/output (I/O) transmission line to propagate a signal tone. The system also includes a non-linearity circuit comprising at least one Josephson junction to provide at least one inductive path of the signal tone in parallel with the at least one Josephson junction. The system further includes an impedance matching network coupled to the I/O transmission line to provide impedance matching of the tone signal between the I/O transmission line and the non-linearity element.

Abstract: One example includes a superconducting bidirectional current driver. The current driver includes a first direction superconducting latch that is activated in response to a first activation signal to provide a first current path of an input current through a bidirectional current load in a first direction. The current driver also includes a second direction superconducting latch that is activated in response to a second activation signal to provide a second current path of the input current through the bidirectional current load in a second direction opposite the first direction.