Patents by Inventor Ofir Degani
Ofir Degani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240243477Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.Type: ApplicationFiled: February 15, 2024Publication date: July 18, 2024Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Marian Verhelst, Yossi Tsfati, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
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Publication number: 20240223416Abstract: A system includes a processor configured to determine a frequency offset between a first local oscillator and a second local oscillator using a combined radio signal received at a first transceiver circuit; wherein the combined radio signal comprises a first signal transmitted by the first transceiver circuit and a second signal transmitted by a second transceiver circuit.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Inventors: Hossein ALAVI, Elan BANIN, Ofir DEGANI, Ashoke RAVI
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Publication number: 20240213947Abstract: A filter includes a plurality of filtering paths. The plurality of filtering paths is driven by a corresponding plurality of local oscillator (LO) signals associated with an LO frequency. Each of the LO signals has a phase of a plurality of phases. Each filtering path of the plurality of filtering paths includes a plurality of signal generation branches. The plurality of signal generation branches is configured to receive a harmonic LO signal based on a fraction of the LO frequency, and generate an LO signal of the corresponding plurality of LO signals associated with the LO frequency using the harmonic LO signal.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Inventors: Run Levinger, SOUMYA GUPTA, SASHANK KRISHNAMURTHY, Ashoke Ravi, Ofir Degani
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Methods and devices for mitigating pulling in a fractional local oscillator signal generation scheme
Patent number: 12021964Abstract: A radio-frequency integrated circuit (RFIC) configured to generate a synthesized clock includes a phase locked loop (PLL) configured to divide down a clock to a non-harmonic frequency; a plurality of multi-phase injection locked clock multipliers (ILCM) directly connected to a plurality of transceiver chains; wherein the PLL is further configured to distribute a divided down clock to at least one of the plurality of multi-phase ILCMs; wherein the plurality of multiphase ILCMs are configured to select a phase of and multiply the divided down clock to synthesize a desired harmonic frequency of the clock and suppress an undesired harmonic frequency of the clock.Type: GrantFiled: December 27, 2019Date of Patent: June 25, 2024Assignee: Intel CorporationInventors: Ashoke Ravi, Ronen Kronfeld, Ofir Degani -
Patent number: 12021608Abstract: Some demonstrative embodiments may include an apparatus including an integrated Radio Head (RH), the integrated RH including an antenna; a transceiver chain to transmit a Radio Frequency (RF) transmit (Tx) signal via the antenna, and to receive an RF Receive (Rx) signal via the antenna; a Physical layer (PHY) time-domain (TD) processor configured to generate a digital PHY TD Rx signal based on the RF Rx signal, and to cause the transceiver chain to transmit the RF Tx signal based on a digital PHY TD Tx signal; and a digital interface to communicate the digital PHY TD Tx signal and the digital PHY TD Rx signal over a digital link.Type: GrantFiled: December 26, 2019Date of Patent: June 25, 2024Assignee: INTEL CORPORATIONInventors: Ofir Degani, Ehud Reshef, Eytan Mann, Ashoke Ravi
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Patent number: 11991265Abstract: A wireless communication device for asymmetrical frequency spreading including a processor configured to receive a frequency band message comprising a maximum difference and a minimum difference, wherein the maximum difference is between a maximum frequency of a sub-band and a signal frequency, and wherein the minimum difference is between the minimum frequency of the sub-band and the signal frequency compare the maximum difference and the minimum difference with each other; and generate a frequency shift based on the comparison.Type: GrantFiled: September 22, 2021Date of Patent: May 21, 2024Assignee: Intel CorporationInventors: Elan Banin, Evgeny Shumaker, Ofir Degani, Rotem Banin, Shahar Gross
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Patent number: 11979177Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.Type: GrantFiled: July 6, 2022Date of Patent: May 7, 2024Assignee: Intel CorporationInventors: Elan Banin, Eytan Mann, Rotem Banin, Ronen Gernizky, Ofir Degani, Igal Kushnir, Shahar Porat, Amir Rubin, Vladimir Volokitin, Elinor Kashani, Dmitry Felsenstein, Ayal Eshkoli, Tal Davidson, Eng Hun Ooi, Yossi Tsfati, Ran Shimon
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Publication number: 20240120929Abstract: The present disclosure relates to a signal generator including: a plurality of interpolators, each interpolator being configured to: receive a first input signal having a first phase, and a second input signal having a second phase; generate a plurality of interpolated signals based on a plurality of interpolations of the input signals, each interpolated signal having a respective phase based on the respective interpolation, and combine the interpolated signals to provide an output signal; the plurality of interpolators including: a first plurality of interpolators, each interpolator being configured to receive as input signals a first reference signal and a second reference signal; and a second plurality of interpolators, each interpolator being configured to receive as first input signal an output signal from an interpolator of the first plurality of interpolators and as second input signal another output signal from another interpolator of the first plurality of interpolators.Type: ApplicationFiled: September 30, 2022Publication date: April 11, 2024Inventors: Ofir DEGANI, Run LEVINGER, Ashoke RAVI
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Patent number: 11955732Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.Type: GrantFiled: December 27, 2022Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
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Publication number: 20240113696Abstract: For example, a phase shifter may include an input to receive an input clock signal having an input frequency and an input phase. For example, the phase shifter may include a quadrature phase-shift generator configured to generate a first signal and a second signal based on the input clock signal, the first and second signals having the input frequency, wherein a phase of the first signal is based on the input phase, wherein a phase of the second signal is shifted by a quadrature phase-shift relative to the phase of the first signal. For example, the phase shifter may include an output to provide an output based on the first signal and the second signal.Type: ApplicationFiled: October 1, 2022Publication date: April 4, 2024Applicant: INTEL CORPORATIONInventors: Elan Banin, Rotem Banin, Ashoke Ravi, Assaf Ben-Bassat, Ofir Degani
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Publication number: 20240113670Abstract: For example, an apparatus may include an input to receive an input signal in a first voltage domain; a multi-mode power amplifier switchable between a plurality of power modes to generate an output signal based on the input signal; and an output to provide the output signal. For example, the multi-mode power amplifier may be configured to provide the output signal in the first voltage domain at a first power mode, and to provide the output signal in a second voltage domain at a second power mode. For example, a maximal voltage of the second voltage domain may be at least two times a maximal voltage of the first voltage domain.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: INTEL CORPORATIONInventors: Ofir Degani, Naor Roi Shay, Assaf Ben-Bassat, Limor Zohar, Yishai Eilat
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Patent number: 11949441Abstract: A transmitter for generating a radio frequency, RF, transmit signal is provided. The transmitter includes signal generation circuitry configured to generate, based on a sequence of first control words each indicating a respective frequency shift with respect to a target frequency of the RF transmit signal, a RF carrier signal with sequentially varying frequency over time in order to frequency spread the RF transmit signal. Further, the transmitter includes modulation circuitry configured to generate the RF transmit signal by modulating the RF carrier signal with a modulation control signal. The transmitter additionally includes modification circuitry configured to generate the modulation control signal by modifying, based on the sequence of first control words, phase information of a baseband signal bearing information to be transmitted or phase information of a signal derived from the baseband signal in order to frequency de-spread the RF transmit signal.Type: GrantFiled: July 23, 2020Date of Patent: April 2, 2024Assignee: Intel CorporationInventors: Elan Banin, Ofir Degani, Rotem Banin, Shahar Gross
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Publication number: 20240097325Abstract: An antenna array architecture is provided for beamforming applications. The antenna array architecture facilitates a compact and wideband dual-polarized beam-switching antenna array architecture, which may be implemented in a cost-effective multi-layer PCB or package. The antenna array architecture is implemented as part of a package substrate having a number of layers. Each of the layers comprises various conductive elements such as conductive segments and/or traces that are disposed thereon in accordance with the respective antenna components.Type: ApplicationFiled: September 19, 2022Publication date: March 21, 2024Inventors: Kexin Hu, Tae Young Yang, Seong-Youp John Suh, Harry Skinner, Ashoke Ravi, Ofir Degani, Ronen Kronfeld
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Patent number: 11923859Abstract: An apparatus for generating a frequency estimate of an output signal includes a reference signal generator configured to generate a reference clock signal. The apparatus includes frequency estimation circuitry configured to generate a cycle count based frequency estimation of the output signal based on the reference clock signal and a clock cycle count of the output signal. The frequency estimation circuitry further generates a fractional frequency estimation of the output signal based on the reference clock signal and a plurality of time-to-digital conversion phase samples of the output signal. The frequency estimation circuitry further generates the frequency estimate of the output signal using the cycle count based frequency estimation within a range and a frequency error determined from the fractional frequency estimation. The plurality of time-to-digital conversion phase samples and the cycle count based frequency estimation use a same number of reference clock cycles of the reference clock signal.Type: GrantFiled: September 25, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Evgeny Shumaker, Sergey Bershansky, Ofir Degani, Run Levinger
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Publication number: 20240056120Abstract: A tunable bandpass low-noise amplifier (LNA). The LNA includes a plurality of N-path filters and a plurality of cascode amplifiers. The cascode amplifiers are configured to amplify an input signal. Each N-path filter is coupled to a different one of the plurality of cascode amplifiers. The plurality of N-path filters are driven by local oscillator (LO) signals having different frequencies, and output nodes of the plurality of cascode amplifiers are coupled in parallel. The frequencies of the LO signals may be symmetrically spaced around a desired frequency (fLO). Each N-path filter may be coupled to a source of the common-gate device of the coupled cascode amplifier. The LO signals may be generated by a digital-to-time converter (DTC)-based frequency synthesizer. The frequencies of the LO signals supplied to the N-path filters may be adjusted to tune the bandwidth of the bandpass LNA.Type: ApplicationFiled: August 12, 2022Publication date: February 15, 2024Inventors: Sashank KRISHNAMURTHY, Ofir DEGANI, Ashoke RAVI
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Patent number: 11902062Abstract: An apparatus for transmitting a bit in addition to a plurality of payload data symbols of a communication protocol is provided. The apparatus comprises an input interface configured to receive information about a bit value of the bit. Further, the apparatus comprises a transmission circuit configured to, if the bit value is a first value, transmit the plurality of payload data symbols at predetermined positions in a data signal as pulses of variable pulse length. The respective pulse length of each of the pulses is selected based on the symbol value of the payload data symbol represented by the respective pulse. If the bit value is a second value, the transmission circuit is configured to transmit a pulse exhibiting a pulse length being longer than a maximum payload data symbol pulse length defined in the communication protocol at the predetermined position of the pulse for the d-th payload data symbol of the plurality of payload data symbols, d=k+i if k+i?z. d=([k+i] mod z) if k+i>z.Type: GrantFiled: December 23, 2019Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Elan Banin, Rotem Banin, Ofir Degani, Eytan Mann
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METHODS AND DEVICES FOR MITIGATING PULLING IN A FRACTIONAL LOCAL OSCILLATOR SIGNAL GENERATION SCHEME
Publication number: 20240048351Abstract: A radio-frequency integrated circuit (RFIC) configured to generate a synthesized clock includes a phase locked loop (PLL) configured to divide down a clock to a non-harmonic frequency; a plurality of multi-phase injection locked clock multipliers (ILCM) directly connected to a plurality of transceiver chains; wherein the PLL is further configured to distribute a divided down clock to at least one of the plurality of multi-phase ILCMs; wherein the plurality of multiphase ILCMs are configured to select a phase of and multiply the divided down clock to synthesize a desired harmonic frequency of the clock and suppress an undesired harmonic frequency of the clock.Type: ApplicationFiled: December 27, 2019Publication date: February 8, 2024Inventors: Ashoke RAVI, Ronen KRONFELD, Ofir DEGANI -
In-package RF waveguides as high bandwidth chip-to-chip interconnects and methods for using the same
Patent number: 11894324Abstract: In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.Type: GrantFiled: November 16, 2021Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Aleksandar Aleksov, Telesphor Kamgaing, Sri Ranga Sai Boyapati, Kristof Darmawikarta, Eyal Fayneh, Ofir Degani, David Levy, Johanna M. Swan -
Patent number: 11870449Abstract: A clock generator calibration system can include a phased-locked loop and a correction circuit. The PLL can generate an output clock signal, and the correction circuit can adjust a frequency signal of the PLL based on a digital signal of the PLL. The digital signal can be generated based on the adjusted frequency signal.Type: GrantFiled: December 28, 2019Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Elan Banin, Yaniv Cohen, Ofir Degani, Igal Kushnir
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Publication number: 20230413195Abstract: A radio-head apparatus can comprise memory to store dithering information of the apparatus. The radio-head can further include radio-head circuitry to generate a clock signal according to the dithering information and to provide a wakeup signal, subsequent to commencement of clock signal generation, to instruct a secondary RH to use the clock signal of the RH. The same wakeup signal is also used to synchronize the finite state machines of both RHs that govern and report the dithering information. Synchronization of the FSM allows estimation of information to be used in the secondary RH for compensation of the clock dithering applied in the primary RH. Other systems and apparatuses are described.Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Inventors: Evgeny Shumaker, Elan Banin, Ofir Degani
