Patents by Inventor Ofir Degani

Ofir Degani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Frequency doubler pulse limiter and methods for limiting pulse widths produced by a frequency doubler
    Patent number: 10958255
    Abstract: This disclosure provides devices and methods for limiting the duration of pulses resulting from frequency modulation so as to provide for better propagation of a frequency doubler output within a communication device. The frequency doubler may be configured to receive a frequency doubler input and produce a modified frequency doubler output, wherein the frequency doubler includes a first flip-flop gate configured to receive a data input, a reset input, and a clock input and produce a first gate output; a first delay control configured to receive the gate output and produce a first delayed control output; and a first logic gate configured to receive the delayed control output and the frequency doubler input and produce a first logic gate output, wherein the modified frequency doubler output is based on the first logic gate output.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Gil Asa, Assaf Ben-Bassat, Ofir Degani, Shahar Gross, Rotem Banin, Uri Grosglik
  • DIGITAL RADIO HEAD CONTROL
    Publication number: 20210067182
    Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 4, 2021
    Inventors: Ashoke Ravi, Jann Benjamin, Satwik Patnaik, Elan Banin, Igal Kushnir, Ofir Degani, Alexandros Margomenos
  • Multiplying delay lock loop (MDLL) and method of averaging ring oscillator signals for jitter compensation
    Patent number: 10840916
    Abstract: Aspects of present disclosure of multiplying delay lock loop (MDLL) circuitry and communication devices are generally described herein. The MDLL circuitry may comprise a multiplexer and a ring oscillator. The ring oscillator may comprise a cascade of delay elements. The multiplexer may receive a reference clock signal and may receive a ring oscillator output signal from a final delay element of the cascade of delay elements. The multiplexer may select, as a ring oscillator input signal, either the reference clock signal or the ring oscillator output signal. The ring oscillator may determine a jitter estimate based at least partly on a comparison between output signals of two particular delay elements of the cascade. The ring oscillator may compensate delay responses of the delay elements of the cascade based at least partly on the jitter estimate.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Ashoke Ravi, Ofir Degani
  • Apparatus, system and method of generating a frequency output with a digitally controlled ring oscillator (DCRO)
    Patent number: 10840923
    Abstract: For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 17, 2020
    Assignee: INTEL IP CORPORATION
    Inventors: Ashoke Ravi, Rotem Banin, Ofir Degani, David Ben-Haim, Yigal Kalmanovich
  • Switched capacitor radio frequency digital power amplifier and radio frequency digital-to-analog converter
    Publication number: 20200321924
    Abstract: A switched capacitor digital power amplifier (DPA) or a digital-to-analog converter (DAC) is disclosed. The DPA/DAC includes a plurality of switched capacitor cells connected in parallel. Each switched capacitor cell includes a capacitor and a switch. The switch selectively drives the capacitor in response to an input digital codeword. The switched capacitor cells are divided into sub-arrays and a series capacitor is inserted in series between two adjacent sub-arrays of switched capacitor cells. All the sub-arrays of switched capacitor cells may be in a unary-coded structure. Alternatively, at least one of the sub-arrays may be in a C-2C structure and at least one another sub-array may be in a unary-coded structure. The switch in the switched capacitor cells is driven by a local oscillator signal, and a phase correction buffer may be added for adjusting a delay of the local oscillator signal supplied to sub-arrays of switched capacitor cells.
    Type: Application
    Filed: December 29, 2017
    Publication date: October 8, 2020
    Inventors: Ali AZAM, Ashoke RAVI, Bassam KHAMAISI, Ofir DEGANI
  • DTC based carrier shift—online calibration
    Patent number: 10788794
    Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Ofir Degani, Elan Banin, Eran Ben Ami
  • Time-to-digital converter, digital phase-locked loop, method for operating a time-to-digital converter, and method for a digital phase-locked loop
    Patent number: 10768580
    Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: September 8, 2020
    Assignee: Intel IP Corporation
    Inventors: Yair Dgani, Michael Kerner, Elan Banin, Evgeny Shumaker, Gil Horovitz, Ofir Degani, Rotem Banin, Aryeh Farber, Rotem Avivi, Eshel Gordon, Tami Sela
  • Detecting a Touch Input to a Surface
    Publication number: 20200241672
    Abstract: A device for detecting a touch input to a surface comprises at least one radar transmitter component configured to transmit electromagnetic radiation in a radio frequency spectrum. The device further comprises at least one radar receiver component configured to receive a portion of the electromagnetic radiation reflected by an object performing the touch input to the surface. The device further comprises a control module configured to receive information related to the portion of the electromagnetic radiation received by the at least one radar receiver component. The control module is further configured to detect the touch input to the surface based on the information related to the portion of the electromagnetic radiation received by the at least one radar receiver component.
    Type: Application
    Filed: August 24, 2017
    Publication date: July 30, 2020
    Inventors: Igal Kushnir, Ofir Degani
  • MULTIPLYING DELAY LOCK LOOP (MDLL) AND METHOD OF AVERAGING RING OSCILLATOR SIGNALS FOR JITTER COMPENSATION
    Publication number: 20200228122
    Abstract: Aspects of present disclosure of multiplying delay lock loop (MDLL) circuitry and communication devices are generally described herein. The MDLL circuitry may comprise a multiplexer and a ring oscillator. The ring oscillator may comprise a cascade of delay elements. The multiplexer may receive a reference clock signal and may receive a ring oscillator output signal from a final delay element of the cascade of delay elements. The multiplexer may select, as a ring oscillator input signal, either the reference clock signal or the ring oscillator output signal. The ring oscillator may determine a jitter estimate based at least partly on a comparison between output signals of two particular delay elements of the cascade. The ring oscillator may compensate delay responses of the delay elements of the cascade based at least partly on the jitter estimate.
    Type: Application
    Filed: August 7, 2017
    Publication date: July 16, 2020
    Inventors: Ashoke Ravi, Ofir Degani
  • Time encoded data communication protocol, apparatus and method for generating and receiving a data signal
    Publication number: 20200212943
    Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.
    Type: Application
    Filed: September 17, 2018
    Publication date: July 2, 2020
    Inventors: Elan Banin, Eytan Mann, Rotem Banin, Ronen Gernizky, Ofir Degani, Igal Kushnir, Shahar Porat, Amir Rubin, Vladimir Volokitin, Elinor Kashani, Dmitry Felsenstein, Ayal Eshkoli, Tal Davidson, Eng Hun Ooi, Yossi Tsfati, Ran Shimon
  • Divider-less fractional PLL architecture
    Patent number: 10659061
    Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Elias Nassar, Eyal Fayneh, Inbar Falkov, Elan Banin, Rotem Banin, Ofir Degani, Samer Nassar
  • IN-PACKAGE RF WAVEGUIDES AS HIGH BANDWIDTH CHIP-TO-CHIP INTERCONNECTS AND METHODS FOR USING THE SAME
    Publication number: 20200118951
    Abstract: In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.
    Type: Application
    Filed: June 19, 2017
    Publication date: April 16, 2020
    Inventors: Aleksandar ALEKSOV, Telesphor KAMGAING, Sri Ranga Sai BOYAPATI, Kristof DARMAWIKARTA, Eyal FAYNEH, Ofir DEGANI, David LEVY, Johanna M. SWAN
  • WIRELESS COMMUNICATION TECHNOLOGY, APPARATUSES, AND METHODS
    Publication number: 20200091608
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Application
    Filed: December 20, 2017
    Publication date: March 19, 2020
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • DTC BASED CARRIER SHIFT - ONLINE CALIBRATION
    Publication number: 20200004207
    Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 2, 2020
    Inventors: Ofir Degani, Elan Banin, Eran Ben Ami
  • Apparatus and a method for generating a radio frequency signal
    Patent number: 10516563
    Abstract: An apparatus for generating a radio frequency signal based on a symbol within a constellation diagram is provided. The constellation diagram is spanned by a first axis representing an in-phase component and an orthogonal second axis representing a quadrature component. The apparatus includes a processing unit configured to select a segment of a plurality of segments of the constellation diagram containing the symbol. The segment is delimited by a third axis and a fourth axis each crossing the origin of the constellation diagram and spanning an opening angle of the segment of less than about 90°. The processing unit is further configured to calculate a first coordinate of the symbol with respect to the third axis, and a second coordinate of the symbol with respect to the fourth axis. The apparatus further includes a plurality of digital-to-analog converter cells configured to generate the radio frequency signal using the first coordinate and the second coordinate.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 24, 2019
    Assignee: Intel IP Corporation
    Inventors: Sebastian Sievert, Ofir Degani, Ashoke Ravi, Rotem Banin
  • TIME-TO-DIGITAL CONVERTER, DIGITAL PHASE-LOCKED LOOP, METH-OD FOR OPERATING A TIME-TO-DIGITAL CONVERTER, AND METHOD FOR A DIGITAL PHASE-LOCKED LOOP
    Publication number: 20190384230
    Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
    Type: Application
    Filed: March 2, 2017
    Publication date: December 19, 2019
    Inventors: Yair Dgani, Michael Kerner, Elan Banin, Evgeny Shumaker, Gil Horovitz, Ofir Degani, Rotem Banin, Aryeh Farber, Rotem Avivi, Eshel Gordon, Tami Sela
  • DIVIDER-LESS FRACTIONAL PLL ARCHITECTURE
    Publication number: 20190334533
    Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.
    Type: Application
    Filed: December 27, 2016
    Publication date: October 31, 2019
    Inventors: Elias Nassar, Eyal Fayneh, Inbar Falkov, Elan Banin, Rotem Banin, Ofir Degani, Samer Nassar
  • DTC based carrier shift—online calibration
    Patent number: 10459407
    Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Ofir Degani, Elan Banin, Eran Ben Ami
  • APPARATUS, SYSTEM AND METHOD OF GENERATING A FREQUENCY OUTPUT WITH A DIGITALLY CONTROLLED RING OSCILLATOR (DCRO)
    Publication number: 20190253058
    Abstract: For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.
    Type: Application
    Filed: September 29, 2016
    Publication date: August 15, 2019
    Applicant: INTEL IP CORPORATION
    Inventors: Ashoke Ravi, Rotem Banin, Ofir Degani, David Ben-Haim, Yigal Kalmanovich
  • Direct digital frequency generation using time and amplitude
    Patent number: 10230520
    Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: March 12, 2019
    Assignee: Intel IP Corporation
    Inventors: Hasnain Lakdawala, Ashoke Ravi, Ofir Degani, Bernd-Ulrich Klepser, Zdravko Boos, Georgios Palaskas, Stefano Pellerano, Paolo Madoglio