Abstract: Provided is a memory mapping method, and particularly provided is a nonvolatile main memory mapping method for managing a nonvolatile main memory. The nonvolatile memory mapping method includes: performing a system call in order to access a file page that is required to operate a process stored in a kernel area of a nonvolatile main memory, wherein both the file page and process are stored in the kernel area of the nonvolatile main memory; and mapping a physical address of the file page to a virtual address of a user area of the nonvolatile main memory.

Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.

Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.

Abstract: Provided are a semiconductor device configured to block a physical diffusion path by forming an oxide layer between barrier layers to prevent impurities from being diffused through the physical diffusion path between the barrier layers, and a method for fabricating the semiconductor device. The semiconductor device includes a gate insulation layer formed on a substrate, a first barrier layer formed on the gate insulation layer, an oxide layer formed on the first barrier layer, the oxide layer including an oxide formed by oxidizing a material included in the first barrier layer, a second barrier layer formed on the oxide layer, a gate electrode formed on the second barrier layer, and source/drains disposed at opposite sides of the gate electrode in the substrate.

Abstract: Provided are methods for fabricating semiconductor devices. The methods for fabricating the semiconductor devices may include forming a first interlayer insulation film including a trench on a substrate, forming a high-k layer along an inner sidewall and a bottom surface of the trench, forming a first work function control film including impurities along the high-k layer, removing the impurities from the first work function control film to reduce surface resistance of the first work function control film by about 30% to about 60% and forming a gate metal in the trench.

Abstract: Provided are methods for fabricating semiconductor devices. The methods for fabricating the semiconductor devices may include forming a first interlayer insulation film including a trench on a substrate, forming a high-k layer along an inner sidewall and a bottom surface of the trench, forming a first work function control film including impurities along the high-k layer, removing the impurities from the first work function control film to reduce surface resistance of the first work function control film by about 30% to about 60% and forming a gate metal in the trench.

Abstract: An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

Abstract: A memory system includes a central processing unit (CPU), a nonvolatile memory electrically coupled to the CPU and a main memory, which is configured to swap an incoming code page for a target code page therein, in response to a first command issued by the CPU. The main memory can be configured to swap the target code page in the main memory to the nonvolatile memory in the event a page capacity of the main memory is at a threshold capacity. The CPU may also be configured to perform a frequency of use analysis on the target code page to determine whether the target code page is to be swapped to the nonvolatile memory or discarded. The incoming code page may be provided by a disk drive storage device and the main memory may be a volatile memory.

Abstract: Provided is a semiconductor device including first, second and third source/drain regions. A first conductive plug in contact with the first source/drain regions, having a first width and a first height, and including a first material is provided. An interlayer insulating layer covering the first conductive plug and the substrate is disposed. A second conductive plug vertically penetrating the interlayer insulating layer to be in contact with the second source/drain regions, having a second width and a second height, and including a second material is provided. A third conductive plug vertically penetrating the interlayer insulating layer to be in contact with the third source/drain regions, having a third width and a third height, and including a third material is disposed. The second material includes a noble metal, a noble metal oxide or a perovskite-based conductive oxide.

Abstract: A data management method for a main memory including a memory controller and a nonvolatile RAM includes; designating code page data temporarily stored in a standby area of the nonvolatile RAM as set, copying the code page data from the standby area to an in-use area of the nonvolatile RAM, designating the code page data stored in the in-use area as reset, and thereafter, during rebooting of a user device incorporating the main memory, invalidating the reset code page data while retaining the set code page data in the nonvolatile RAM.

Abstract: Provided is a memory mapping method, and particularly provided is a nonvolatile main memory mapping method for managing a nonvolatile main memory. The nonvolatile memory mapping method includes: performing a system call in order to access a file page that is required to operate a process stored in a kernel area of a nonvolatile main memory, wherein both the file page and process are stored in the kernel area of the nonvolatile main memory; and mapping a physical address of the file page to a virtual address of a user area of the nonvolatile main memory.

Abstract: Provided is a micro-journaling for a file system based on a non-volatile memory. A system includes a central processing unit (CPU), a main memory realized in a non-volatile memory, and a storage device. The file system resides in the non-volatile main memory, and micro-journaling is performed. The micro-journaling includes a commit operation for flushing data of a CPU cache to a user space, and a checkpoint operation performed per page unit while a file write operation is performed through a system call. Since the non-volatile main memory is capable of permanently storing data, a data double duplication process for reliability of the file system may be removed, and the file system is recovered from a sudden power-off of the system by using the micro-journaling for recording logging information while the file write operation is performed and checking a point.

Abstract: A nonvolatile memory device includes a memory cell array comprising memory cells connected to bit lines and word lines; a word line decoder configured to apply word line voltages to the word lines; a bit line selector configured to select at least one bit line of the bit lines; a control logic configured to control the word line decoder and the bit line selector so that write data is programmed in the memory cell array; and a sudden power off (SPO) detection circuit, wherein the SPO detection circuit comprises: a sensing cell; a first driver configured to provide a first voltage to the sensing cell; and a second driver configured to provide a second voltage to the sensing cell, wherein a program state of the sensing cell becomes different depending on an order or a time difference between the first driver and the second driver being powered off.

Abstract: A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5 eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials.

Abstract: A nonvolatile memory device includes a memory cell array comprising memory cells connected to bit lines and word lines; a word line decoder configured to apply word line voltages to the word lines; a bit line selector configured to select at least one bit line of the bit lines; a control logic configured to control the word line decoder and the bit line selector so that write data is programmed in the memory cell array; and a sudden power off (SPO) detection circuit, wherein the SPO detection circuit comprises: a sensing cell; a first driver configured to provide a first voltage to the sensing cell; and a second driver configured to provide a second voltage to the sensing cell, wherein a program state of the sensing cell becomes different depending on an order or a time difference between the first driver and the second driver being powered off.

Abstract: A method of writing data in a resistive memory device includes performing a test operation to distinguish normal memory cells from weak memory cells, during a write operation directed to normal memory cells using a write current and during a weak write operation directed to weak memory cells using a higher write current.

Abstract: A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5 eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials.

Abstract: A data management method for a main memory including a memory controller and a nonvolatile RAM includes; designating code page data temporarily stored in a standby area of the nonvolatile RAM as set, copying the code page data from the standby area to an in-use area of the nonvolatile RAM, designating the code page data stored in the in-use area as reset, and thereafter, during rebooting of a user device incorporating the main memory, invalidating the reset code page data while retaining the set code page data in the nonvolatile RAM.

Abstract: Disclosed is a method of booting a user device including a nonvolatile random access memory (RAM) and a mode register. The method includes reading a Basic Input/Output System (BIOS) refresh setting during a booting operation, and setting the mode register to a refresh timing mode of the nonvolatile RAM according to the BIOS refresh setting. The refresh timing mode selectively includes a refresh inactivation mode for inactivating a refresh operation of the nonvolatile RAM or a refresh execution mode of multiple refresh execution modes having corresponding different refresh periods for activating the refresh operation of the nonvolatile RAM.

Abstract: A memory system includes a central processing unit (CPU), a nonvolatile memory electrically coupled to the CPU and a main memory, which is configured to swap an incoming code page for a target code page therein, in response to a first command issued by the CPU. The main memory can be configured to swap the target code page in the main memory to the nonvolatile memory in the event a page capacity of the main memory is at a threshold capacity. The CPU may also be configured to perform a frequency of use analysis on the target code page to determine whether the target code page is to be swapped to the nonvolatile memory or discarded. The incoming code page may be provided by a disk drive storage device and the main memory may be a volatile memory.