Patents by Inventor Oh-seong Kwon

Oh-seong Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130208535
    Abstract: A method of writing data in a resistive memory device includes performing a test operation to distinguish normal memory cells from weak memory cells, during a write operation directed to normal memory cells using a write current and during a weak write operation directed to weak memory cells using a higher write current.
    Type: Application
    Filed: September 11, 2012
    Publication date: August 15, 2013
    Inventors: OH-SEONG KWON, JIN-HYUN KIM, HYUN-HO CHOI
  • Publication number: 20120299072
    Abstract: Provided is a semiconductor device including first, second and third source/drain regions. A first conductive plug in contact with the first source/drain regions, having a first width and a first height, and including a first material is provided. An interlayer insulating layer covering the first conductive plug and the substrate is disposed. A second conductive plug vertically penetrating the interlayer insulating layer to be in contact with the second source/drain regions, having a second width and a second height, and including a second material is provided. A third conductive plug vertically penetrating the interlayer insulating layer to be in contact with the third source/drain regions, having a third width and a third height, and including a third material is disposed. The second material includes a noble metal, a noble metal oxide or a perovskite-based conductive oxide.
    Type: Application
    Filed: March 21, 2012
    Publication date: November 29, 2012
    Inventors: WAN-DON KIM, Seung-Hwan Lee, Beom-Seok Kim, Kyu-Ho Cho, Oh-Seong Kwon, Geun-Kyu Choi, Ji-Eun Lim, Yong-Suk Tak
  • Publication number: 20120119327
    Abstract: A capacitor in a semiconductor memory device comprises a lower electrode on a substrate that is formed of a conductive metal oxide having a rutile crystalline structure, a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and includes impurities for reducing a leakage current, and an upper electrode on the titanium oxide dielectric layer. A method of forming a capacitor in a semiconductor device comprise steps of forming a lower electrode on a substrate that includes a conductive metal oxide having a rutile crystalline structure, forming a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and impurities for reducing a leakage current, and forming an upper electrode on the titanium oxide dielectric layer.
    Type: Application
    Filed: September 21, 2011
    Publication date: May 17, 2012
    Inventors: Oh-Seong Kwon, Kyu-Ho Cho, Wan-Don Kim, Beom-Seok Kim, Yong-Suk Tak
  • Publication number: 20120086014
    Abstract: A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials.
    Type: Application
    Filed: July 14, 2011
    Publication date: April 12, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wan-Don Kim, Beom-Seok Kim, Yong-Suk Tak, Kyu-Ho Cho, Seung-Hwan Lee, Oh-Seong Kwon, Geun-Kyu Choi
  • Publication number: 20110242727
    Abstract: A capacitor may include a lower electrode structure, a dielectric layer and an upper electrode structure. The lower electrode structure may include a first lower pattern, a first deformation-preventing layer pattern and a second lower pattern. The first lower pattern may have a cylindrical shape. The first deformation-preventing layer pattern may be formed on an inner surface of the first lower pattern. The second lower pattern may be formed on the first deformation-preventing layer pattern. The dielectric layer may be formed on the lower electrode structure. The upper electrode structure may be formed on the dielectric layer. Thus, the capacitor may have a high capacitance and improved electrical characteristics.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 6, 2011
    Inventors: Wan-Don KIM, Beom-Seok Kim, Jong-Cheol Lee, Kyu-Ho Cho, Jin-Yong Kim, Oh-Seong Kwon, Yong-Suk Tak
  • Patent number: 7781819
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-don Kim, Jin-yong Kim, Yong-suk Tak, Jung-hee Chung, Ki-chul Kim, Oh-seong Kwon
  • Publication number: 20100209595
    Abstract: In a method of forming a strontium ruthenate thin film using water vapor as an oxidizing agent, a strontium source and a ruthenium source are used. The strontium source includes a cyclopentadienyl (Cp) ligand, an alkoxide ligand, an alkyl ligand, an amide ligand or a halide ligand, and the ruthenium source includes a beta diketonate ligand.
    Type: Application
    Filed: February 19, 2010
    Publication date: August 19, 2010
    Inventors: Oh-Seong Kwon, Kyu-Ho Cho, Jung-Hee Chung, Jin-Yong Kim, Wan-Don Kim, Youn-Soo Kim, Yong-Suk Tak
  • Publication number: 20100196592
    Abstract: In a method of fabricating a capacitor, a lower electrode is formed, and a dielectric layer is formed on the lower electrode. An upper electrode is foamed on the dielectric layer opposite the lower electrode. A low-temperature capping layer is formed on the upper electrode at a temperature of less than about 300° C. Related devices and fabrication methods are also discussed.
    Type: Application
    Filed: February 3, 2010
    Publication date: August 5, 2010
    Inventors: Wan-Don Kim, Kyu-Ho Cho, Jin-Yong Kim, Jae-Hyoung Choi, Jae-Soon Lim, Oh-Seong Kwon, Beom-Seok Kim, Yong-Suk Tak
  • Publication number: 20090072350
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.
    Type: Application
    Filed: November 13, 2008
    Publication date: March 19, 2009
    Inventors: Wan-don Kim, Jin-yong Kim, Yong-suk Tak, Jung-hee Chung, Ki-chul Kim, Oh-seong Kwon