Patents by Inventor OhHan Kim
OhHan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8709935Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.Type: GrantFiled: February 15, 2013Date of Patent: April 29, 2014Assignee: STATS ChipPAC, Ltd.Inventors: DaeSik Choi, OhHan Kim, SungWon Cho
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Publication number: 20130264705Abstract: A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.Type: ApplicationFiled: May 31, 2013Publication date: October 10, 2013Inventors: KiYoun Jang, DaeSik Choi, OhHan Kim, DongSoo Moon
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Patent number: 8519544Abstract: A semiconductor device can include a carrier substrate, and a first semiconductor die disposed on a surface of the carrier substrate. An encapsulant can be disposed over the first semiconductor die and the carrier substrate. The semiconductor device can include first vias disposed through the encapsulant as well as second vias disposed through the encapsulant to expose first contact pads. The first contact pads are on upper surfaces of the first semiconductor die. The semiconductor device can include conductive pillars that fill the first vias, and first conductive metal vias (CMVs) that fill the second vias. The conductive pillar can include a first conductive material, and the first CMVs can be in contact with the first contact pads. The semiconductor device can include a conductive layer disposed over the encapsulant. The conductive layer can electrically connect one of the first CMVs with one of the conductive pillars.Type: GrantFiled: August 9, 2012Date of Patent: August 27, 2013Assignee: STATS Chip PAC, Ltd.Inventors: OhHan Kim, SungWon Cho, DaeSik Choi, KyuWon Lee, DongSoo Moo
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Patent number: 8519536Abstract: A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.Type: GrantFiled: November 30, 2012Date of Patent: August 27, 2013Assignee: STATS ChipPAC, Ltd.Inventors: KiYoun Jang, DaeSik Choi, OhHan Kim, DongSoo Moon
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Patent number: 8409979Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.Type: GrantFiled: May 31, 2011Date of Patent: April 2, 2013Assignee: STATS ChipPAC, Ltd.Inventors: DaeSik Choi, OhHan Kim, SungWon Cho
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Publication number: 20130056862Abstract: A semiconductor device has a substrate including a recess and a peripheral portion with through conductive vias. A first semiconductor die is mounted over the substrate and within the recess. A planar heat spreader is mounted over the substrate and over the first semiconductor die. The planar heat spreader has openings around a center portion of the planar heat spreader and aligned over the peripheral portion of the substrate. A second semiconductor die is mounted over the center portion of the planar heat spreader. A third semiconductor die is mounted over the second semiconductor die. First and second pluralities of bond wires extend from the second and third semiconductor die, respectively, through the openings in the planar heat spreader to electrically connect to the through conductive vias. An encapsulant is deposited over the substrate and around the planar heat spreader.Type: ApplicationFiled: September 7, 2011Publication date: March 7, 2013Applicant: STATS CHIPPAC, LTD.Inventors: OhHan Kim, WonJun Ko, DaeSik Choi
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Publication number: 20130049188Abstract: A semiconductor device has a semiconductor die mounted to a substrate. The semiconductor die and substrate are disposed within a mold chase with a releasing layer disposed over the semiconductor die. A MUF material is deposited around the semiconductor die, releasing layer, and substrate through an opening in the mold chase. The opening in the mold chase is located in an upper mold support of the mold chase. A recess is formed in the MUF material by removing the releasing layer. A TIM is formed in the recess of the MUF material. The TIM is substantially coplanar with the MUF material. A heat spreader is formed over the TIM material. The heat spreader can be formed within the recess of the MUF material over the TIM. A plurality of bumps is formed over a surface of the substrate opposite the semiconductor die.Type: ApplicationFiled: August 25, 2011Publication date: February 28, 2013Applicant: STATS CHIPPAC, LTD.Inventors: DaeSik Choi, OhHan Kim, MinWook Yu
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Patent number: 8367467Abstract: A method of making a semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.Type: GrantFiled: April 21, 2010Date of Patent: February 5, 2013Assignee: STATS ChipPAC, Ltd.Inventors: KiYoun Jang, DaeSik Choi, OhHan Kim, DongSoo Moon
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Publication number: 20120306104Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: STATS CHIPPAC, LTD.Inventors: DaeSik Choi, OhHan Kim, SungWon Cho
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Publication number: 20120306097Abstract: A semiconductor device can include a carrier substrate, and a first semiconductor die disposed on a surface of the carrier substrate. An encapsulant can be disposed over the first semiconductor die and the carrier substrate. The semiconductor device can include first vias disposed through the encapsulant as well as second vias disposed through the encapsulant to expose first contact pads. The first contact pads are on upper surfaces of the first semiconductor die. The semiconductor device can include conductive pillars that fill the first vias, and first conductive metal vias (CMVs) that fill the second vias. The conductive pillar can include a first conductive material, and the first CMVs can be in contact with the first contact pads. The semiconductor device can include a conductive layer disposed over the encapsulant. The conductive layer can electrically connect one of the first CMVs with one of the conductive pillars.Type: ApplicationFiled: August 9, 2012Publication date: December 6, 2012Applicant: STATS CHIPPAC, LTD.Inventors: OhHan Kim, SungWon Cho, DaeSik Choi, KyuWon Lee, DongSoo Moo
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Publication number: 20120292751Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.Type: ApplicationFiled: August 7, 2012Publication date: November 22, 2012Applicant: STATS CHIPPAC, LTD.Inventors: OhHan Kim, SunMi Kim, KyungHoon Lee
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Publication number: 20120241941Abstract: A semiconductor device includes a substrate with conductive traces. A semiconductor die is mounted with an active surface oriented toward the substrate. An underfill material is deposited between the semiconductor die and substrate. A recess is formed in an interior portion of the semiconductor die that extends from a back surface of the semiconductor die opposite the active surface partially through the semiconductor die such that a peripheral portion of the back surface of the semiconductor die is offset with respect to a depth of the recess. A thermal interface material (TIM) is deposited over the semiconductor die and into the recess such that the TIM in the recess is laterally supported by the peripheral portion of the semiconductor die to reduce flow of the TIM away from the semiconductor die. A heat spreader including protrusions is mounted over the semiconductor die and contacts the TIM.Type: ApplicationFiled: March 21, 2011Publication date: September 27, 2012Applicant: STATS CHIPPAC, LTD.Inventors: OhHan Kim, YongHee Kang, KyungHoon Lee
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Patent number: 8273604Abstract: A semiconductor device can include a carrier substrate, and a first semiconductor die disposed on a surface of the carrier substrate. An encapsulant can be disposed over the first semiconductor die and the carrier substrate. The semiconductor device can include first vias disposed through the encapsulant as well as second vias disposed through the encapsulant to expose first contact pads. The first contact pads are on upper surfaces of the first semiconductor die. The semiconductor device can include conductive pillars that fill the first vias, and first conductive metal vias (CMVs) that fill the second vias. The conductive pillar can include a first conductive material, and the first CMVs can be in contact with the first contact pads. The semiconductor device can include a conductive layer disposed over the encapsulant. The conductive layer can electrically connect one of the first CMVs with one of the conductive pillars.Type: GrantFiled: February 22, 2011Date of Patent: September 25, 2012Assignee: STAT ChipPAC, Ltd.Inventors: OhHan Kim, SungWon Cho, DaeSik Choi, KyuWon Lee, DongSoo Moo
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Patent number: 8264059Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.Type: GrantFiled: February 2, 2011Date of Patent: September 11, 2012Assignee: STATS ChipPAC, Ltd.Inventors: OhHan Kim, SunMi Kim, KyungHoon Lee
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Publication number: 20120211892Abstract: A semiconductor device can include a carrier substrate, and a first semiconductor die disposed on a surface of the carrier substrate. An encapsulant can be disposed over the first semiconductor die and the carrier substrate. The semiconductor device can include first vias disposed through the encapsulant as well as second vias disposed through the encapsulant to expose first contact pads. The first contact pads are on upper surfaces of the first semiconductor die. The semiconductor device can include conductive pillars that fill the first vias, and first conductive metal vias (CMVs) that fill the second vias. The conductive pillar can include a first conductive material, and the first CMVs can be in contact with the first contact pads. The semiconductor device can include a conductive layer disposed over the encapsulant. The conductive layer can electrically connect one of the first CMVs with one of the conductive pillars.Type: ApplicationFiled: February 22, 2011Publication date: August 23, 2012Applicant: STATS CHIPPAC, LTD.Inventors: OhHan Kim, SungWon Cho, DaeSik Choi, KyuWon Lee, DongSoo Moo
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Publication number: 20120153452Abstract: A semiconductor device is made by forming a first active device on a first side of a semiconductor wafer. A first insulating layer is formed over the first side of the wafer. A first conductive layer is formed over the first insulating layer. A first interconnect structure is formed over the first insulating layer and first conductive layer. A temporary carrier is mounted to the first interconnect structure. A second active device is formed on a second side of the semiconductor wafer. A second insulating layer is formed over the second side of the wafer. A second conductive layer is formed over the second insulating layer. A second interconnect structure is formed over the second insulating layer and second conductive layer. The temporary carrier is removed, leaving a double-sided semiconductor device. The double-sided semiconductor device is enclosed in a package with the first and second interconnect structures electrically connected.Type: ApplicationFiled: February 29, 2012Publication date: June 21, 2012Applicant: STATS CHIPPAC, LTD.Inventors: OhHan Kim, JoungUn Park, SunMi Kim
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Patent number: 8137995Abstract: A semiconductor device is made by forming a first active device on a first side of a semiconductor wafer. A first insulating layer is formed over the first side of the wafer. A first conductive layer is formed over the first insulating layer. A first interconnect structure is formed over the first insulating layer and first conductive layer. A temporary carrier is mounted to the first interconnect structure. A second active device is formed on a second side of the semiconductor wafer. A second insulating layer is formed over the second side of the wafer. A second conductive layer is formed over the second insulating layer. A second interconnect structure is formed over the second insulating layer and second conductive layer. The temporary carrier is removed, leaving a double-sided semiconductor device. The double-sided semiconductor device is enclosed in a package with the first and second interconnect structures electrically connected.Type: GrantFiled: December 11, 2008Date of Patent: March 20, 2012Assignee: STATS ChipPAC, Ltd.Inventors: OhHan Kim, JoungUn Park, SunMi Kim
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Publication number: 20110260316Abstract: A semiconductor device has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.Type: ApplicationFiled: April 21, 2010Publication date: October 27, 2011Applicant: STATS CHIPPAC, LTD.Inventors: KiYoun Jang, DaeSik Choi, OhHan Kim, DongSoo Moon
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Publication number: 20110121432Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.Type: ApplicationFiled: February 2, 2011Publication date: May 26, 2011Applicant: STATS CHIPPAC, LTD.Inventors: OhHan Kim, SunMi Kim, KyungHoon Lee
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Patent number: 7906371Abstract: A shielded semiconductor device is made by embedding a ground shield between layers of a substrate. Semiconductor die are mounted to the substrate over the ground shields. An encapsulant is formed over the semiconductor die and substrate. The encapsulant is diced to form dicing channels between the semiconductor die. A plurality of openings is drilled into the substrate along the dicing channels down through the ground shield on each side of the semiconductor die. A top shield is formed over the semiconductor die. The openings in the substrate are filled with a shielding material to electrically and mechanically connect the top shield to the ground shield. The substrate is singulated to separate the semiconductor die with top shield and ground shield into individual semiconductor devices. IPDs in the semiconductor die generate electromagnetic interference which is blocked by the respective top shield and ground shield.Type: GrantFiled: May 28, 2008Date of Patent: March 15, 2011Assignee: STATS ChipPAC, Ltd.Inventors: OhHan Kim, SunMi Kim, KyungHoon Lee