Patents by Inventor Oleg Dadashev
Oleg Dadashev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230268023Abstract: A method of operating a memory device includes: supplying one or more supply voltages to a memory array; and monitoring the one or more supply voltages, which includes: selecting, from the one or more supply voltages, a selected supply voltage; converting, using an analog-to-digital converter (ADC), an internal reference voltage of the memory device and a scaled version of the selected supply voltage into one or more digital values; generating a calibrated measurement result using the one or more digital values; and determining whether the calibrated measurement result is within a pre-determined range.Type: ApplicationFiled: July 12, 2022Publication date: August 24, 2023Inventors: Yoram Betser, Oleg Dadashev, Kobi Danon
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Patent number: 11405026Abstract: Embodiments of the present disclosure provide systems and methods of reducing the EMI effect generated by such analog blocks. By varying the clock frequency in time of oscillators used by such analog blocks, the EMI energy may be spread over a wide spectrum range thereby reducing the peak energy for the main frequency. To achieve this, the oscillator frequency is directly varied using analog mechanisms. The mechanisms may be based on a synchronized method for increasing/decreasing the current that is charging/discharging the oscillator capacitor. The frequency variation may be achieved by analog control of the extra charge/discharge current.Type: GrantFiled: January 29, 2021Date of Patent: August 2, 2022Assignee: Infineon Technologies LLCInventors: Oleg Dadashev, Yoram Betser
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Publication number: 20220052677Abstract: Embodiments of the present disclosure provide systems and methods of reducing the EMI effect generated by such analog blocks. By varying the clock frequency in time of oscillators used by such analog blocks, the EMI energy may be spread over a wide spectrum range thereby reducing the peak energy for the main frequency. To achieve this, the oscillator frequency is directly varied using analog mechanisms. The mechanisms may be based on a synchronized method for increasing/decreasing the current that is charging/discharging the oscillator capacitor. The frequency variation may be achieved by analog control of the extra charge/discharge current.Type: ApplicationFiled: January 29, 2021Publication date: February 17, 2022Applicant: Infineon Technolgies LLCInventors: Oleg Dadashev, Yoram Betser
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Patent number: 9921592Abstract: Described is an apparatus which comprises: a bandgap core to provide a control signal; and an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at an output node.Type: GrantFiled: September 9, 2013Date of Patent: March 20, 2018Assignee: INTEL CORPORATIONInventors: Joseph Shor, George L. Geannopoulos, Fabrice Paillet, Lan D. Vu, Oleg Dadashev
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Publication number: 20160246315Abstract: Described is an apparatus which comprises: a bandgap core to provide a control signal; and an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at an output node.Type: ApplicationFiled: September 9, 2013Publication date: August 25, 2016Inventors: Joseph SHOR, George L. GEANNOPOULOS, Fabrice PAILLET, Lan D. VU, Oleg DADASHEV
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Patent number: 8593881Abstract: The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.Type: GrantFiled: November 22, 2011Date of Patent: November 26, 2013Assignee: Spansion Israel LtdInventors: Yaal Horesh, Oleg Dadashev, Yoram Betser, Avri Harush
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Publication number: 20120063238Abstract: The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.Type: ApplicationFiled: November 22, 2011Publication date: March 15, 2012Inventors: Yaal Horesh, Oleg Dadashev, Yoram Betser, Avri Harush
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Patent number: 8098525Abstract: The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.Type: GrantFiled: September 17, 2008Date of Patent: January 17, 2012Assignee: Spansion Israel LtdInventors: Yaal Horesh, Oleg Dadashev, Yoram Betser, Avri Harush
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Patent number: 7755938Abstract: Disclosed is a method of reducing the neighbor effect while reading data in a non-volatile memory array. The method includes sensing adjacent memory cells. The sensing of the two adjacent cells is performed substantially simultaneously and through at least a partially shared sensing path.Type: GrantFiled: April 19, 2004Date of Patent: July 13, 2010Assignee: Saifun Semiconductors Ltd.Inventors: Shahar Atir, Oleg Dadashev, Yair Sofer, Eduardo Maayan
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Patent number: 7605579Abstract: The present invention is a method and apparatus for regulating current consumption and output current of a charge pump. According to some embodiments of the present invention, a first current coming into the charge pump and a second current coming into a driver of at least one of one or more stages of the charge pump is measured. A control loop may regulate one or more parameters of the charge pump and/or a load connected to the charge pump, such as by adjusting one or more of: a supply voltage; a stage's voltage; the stage's frequency and/or duty-cycle; and the number of stages.Type: GrantFiled: November 21, 2006Date of Patent: October 20, 2009Assignee: Saifun Semiconductors Ltd.Inventors: Yoram Betser, Alexander Kushnarenko, Oleg Dadashev
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Patent number: 7532529Abstract: A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.Type: GrantFiled: August 14, 2006Date of Patent: May 12, 2009Assignee: Saifun Semiconductors Ltd.Inventors: Oleg Dadashev, Yoram Betser, Eduardo Maayan
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Publication number: 20090073774Abstract: The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines may be selected according to a pre-defined table per each address. The selection of the global bitlines may be done according to whether these global bitlines will interfere with the pipe during the next read cycle.Type: ApplicationFiled: September 17, 2008Publication date: March 19, 2009Inventors: Yaal Horesh, Oleg Dadashev, Yoram Betser, Avri Harush
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Publication number: 20080094127Abstract: Measuring and controlling current consumption and output current of a charge pump by measuring a first current coming into the charge pump; and measuring a second current coming into a driver for at least one of the one or more stages of the charge pump. A control loop may one or more parameters of the charge pump and/or a load connected to the charge pump, such as by adjusting one or more of: a supply voltage; a stage's voltage; the stage's frequency and/or duty-cycle; and the number of stages, or by decreasing the current consumption by adjusting a load connected to the output of the charge pump pipe. The first and second currents may be compared with first and second reference currents. A load connected to the charge pump may comprise non-volatile memory cells, and the charge pump may be implemented on a same integrated circuit chip as the memory cells.Type: ApplicationFiled: November 21, 2006Publication date: April 24, 2008Inventors: Yoram Betser, Alexander Kushnarenko, Oleg Dadashev
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Patent number: 7233192Abstract: A method includes controlling the connection of a charge pump output to a load capacitor as a function of activation control signals to an oscillator controlling the charge pump. A charge pump system includes a charge pump, an oscillator, a switching element and an enable signal generator. The switching element connects and disconnects the charge pump from a load capacitor. The enable signal generator is connected to the oscillator and to the switching element and enables and disables the oscillator and the switching element as a function of the output of the charge pump.Type: GrantFiled: April 6, 2005Date of Patent: June 19, 2007Assignee: Saifun Semiconductors LtdInventor: Oleg Dadashev
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Patent number: 7221138Abstract: A method for measuring output current of a charge pump, the method including providing a charge pump including a plurality of n charge pump stages, wherein an output of stage n?1(Von?1) is output to stage n, an output voltage of stage n being referred to as charge pump voltage output Vout, connecting an additional output pass device to the output of stage n?1, an output voltage of the additional output pass device being referred to as Voutm, forcing Voutm to be at least approximately equal to Vout, drawing at least one of output voltage (Voutm) and output current (Ioutm) from the additional output pass device, measuring Ioutm (e.g., comparing Ioutm with a reference current), and correlating Iout with Ioutm.Type: GrantFiled: September 27, 2005Date of Patent: May 22, 2007Assignee: Saifun Semiconductors LtdInventor: Oleg Dadashev
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Patent number: 7202654Abstract: A high voltage regulator including a current mirror including a pair of transistors, one of the transistors being connected to a node that outputs an output voltage Vout, a diode stack that includes a plurality of serially connected transistors T0, T1, T2, . . .Type: GrantFiled: September 27, 2005Date of Patent: April 10, 2007Assignee: Saifun Semiconductors LtdInventors: Oleg Dadashev, Alexander Kushnarenko
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Publication number: 20070069714Abstract: A method for measuring output current of a charge pump, the method including providing a charge pump including a plurality of n charge pump stages, wherein an output of stage n?1 (Von-1) is output to stage n, an output voltage of stage n being referred to as charge pump voltage output Vout, connecting an additional output pass device to the output of stage n?1, an output voltage of the additional output pass device being referred to as Voutm, forcing Voutm to be at least approximately equal to Vout, drawing at least one of output voltage (Voutm) and output current (Ioutm) from the additional output pass device, measuring Ioutm (e.g., comparing Ioutm with a reference current), and correlating Iout with Ioutm.Type: ApplicationFiled: September 27, 2005Publication date: March 29, 2007Applicant: Saifun Semiconductors, Ltd.Inventor: Oleg Dadashev
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Publication number: 20070069711Abstract: A high voltage regulator including a current mirror including a pair of transistors, one of the transistors being connected to a node that outputs an output voltage Vout, a diode stack that includes a plurality of serially connected transistors T0, T1, T2, . . .Type: ApplicationFiled: September 27, 2005Publication date: March 29, 2007Applicant: Saifun Semiconductors, Ltd.Inventors: Oleg Dadashev, Alexander Kushnarenko
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Publication number: 20060285402Abstract: A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.Type: ApplicationFiled: August 14, 2006Publication date: December 21, 2006Applicant: SAIFUN SEMICONDUCTORS LTD.Inventors: Oleg Dadashev, Yoram Betser, Eduardo Maayan
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Patent number: 7142464Abstract: A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.Type: GrantFiled: March 29, 2004Date of Patent: November 28, 2006Assignee: Saifun Semiconductors Ltd.Inventor: Oleg Dadashev