Patents by Inventor Oleg Dadashev
Oleg Dadashev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7142464Abstract: A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.Type: GrantFiled: March 29, 2004Date of Patent: November 28, 2006Assignee: Saifun Semiconductors Ltd.Inventor: Oleg Dadashev
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Publication number: 20060226890Abstract: A method includes controlling the connection of a charge pump output to a load capacitor as a function of activation control signals to an oscillator controlling the charge pump. A charge pump system includes a charge pump, an oscillator, a switching element and an enable signal generator. The switching element connects and disconnects the charge pump from a load capacitor. The enable signal generator is connected to the oscillator and to the switching element and enables and disables the oscillator and the switching element as a function of the output of the charge pump.Type: ApplicationFiled: April 6, 2005Publication date: October 12, 2006Inventor: Oleg Dadashev
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Publication number: 20050232024Abstract: There is provided in accordance with embodiments of the present invention a method of reducing the neighbor effect in reading data in a non-volatile memory array by sensing adjacent memory cells in a virtual ground array of memory cells comprising sensing substantially simultaneously a state of adjacent memory cells, wherein a bit stored in a charge trapping region of each cell of the adjacent memory cells is in an identical state.Type: ApplicationFiled: April 19, 2004Publication date: October 20, 2005Inventors: Shahar Atir, Oleg Dadashev, Yair Sofer, Eduardo Maayan
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Patent number: 6836443Abstract: A sensing system for a memory cell in a memory array includes a current integrator circuit configured to integrate a read current through the memory cell and a reference current through a reference memory cell. The integration process creates a set of differential measurement voltages that can be used to determine the state of the memory cell. By integrating the read current to obtain a measurement voltage, rather than directly comparing the read current to a reference current, the sensing system can use lower supply voltages than conventional sensing systems. In addition, because the measurement voltages are generated by integrating the read current over time, sensing operations are less sensitive to supply voltage fluctuations and the accuracy. Also, for memory cells that exhibit small read currents, the accuracy of sensing operations can be increased by increasing the period of integration.Type: GrantFiled: January 14, 2003Date of Patent: December 28, 2004Assignee: Tower Semiconductor Ltd.Inventor: Oleg Dadashev
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Publication number: 20040218426Abstract: A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.Type: ApplicationFiled: March 29, 2004Publication date: November 4, 2004Inventor: Oleg Dadashev
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Publication number: 20040136256Abstract: A sensing system for a memory cell in a memory array includes a current integrator circuit configured to integrate a read current through the memory cell and a reference current through a reference memory cell. The integration process creates a set of differential measurement voltages that can be used to determine the state of the memory cell. By integrating the read current to obtain a measurement voltage, rather than directly comparing the read current to a reference current, the sensing system can use lower supply voltages than conventional sensing systems. In addition, because the measurement voltages are generated by integrating the read current over time, sensing operations are less sensitive to supply voltage fluctuations and the accuracy. Also, for memory cells that exhibit small read currents, the accuracy of sensing operations can be increased by increasing the period of integration.Type: ApplicationFiled: January 14, 2003Publication date: July 15, 2004Applicant: Tower Semiconductor Ltd.Inventor: Oleg Dadashev
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Patent number: 6469929Abstract: A method for sensing the state of a memory cell includes both dynamic and static clamping of the bit line coupled to a memory cell. This dual clamping configuration/operation ensures a quick charge of the bit line while eliminating overcharging of the bit line. Thus, sensing the state of the memory cell is substantially independent of the size of the memory array. A sensing system for sensing the state of a memory cell can include a system bit line coupled to a terminal of the memory cell, a charge initiation device for activating a charge operation on the system bit line, and a control unit connected between the system bit line and the charge initiation device. The control unit includes a static clamp to charge the system bit line to a first predetermined voltage and a dynamic clamp to charge the system bit line to a second predetermined voltage.Type: GrantFiled: August 21, 2001Date of Patent: October 22, 2002Assignee: Tower Semiconductor Ltd.Inventors: Alexander Kushnarenko, Oleg Dadashev
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Patent number: 6456557Abstract: A memory device includes a voltage regulator that compensates for resistance variations in the bit line control (multiplexing) circuit used to access the memory cells by including in its feedback path an emulated multiplexing circuit having an identical resistance to that of the multiplexing circuit. The voltage regulator also includes a differential amplifier, a pull-up transistor for generating a reference voltage, and a first clamp transistor controlled by the reference voltage to pass a desired voltage level to the multiplexing circuit. The feedback path incorporates the emulator circuit between a second clamp transistor and a voltage divider. Because the emulation and multiplexing circuits have the same resistance, the voltage passed to the voltage divider is essentially identical to the voltage passed by the multiplexing circuit to a selected memory cell, thereby allowing the voltage regulator to produce an optimal voltage level at the selected memory cell.Type: GrantFiled: August 28, 2001Date of Patent: September 24, 2002Assignee: Tower Semiconductor LTDInventors: Oleg Dadashev, Kyra Jacob
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Patent number: 6448822Abstract: A comparator circuit that transforms a difference between two input voltage signals into differential branch currents that are independent of the two input voltage signals. In one embodiment, the comparator circuit utilizes an adaptive bias voltage circuit and a cascode stage to generate the differential branch currents that are applied to a conventional CMOS latch. The adaptive bias voltage circuit utilizes a current source and the two input voltages to generate a bias voltage that is directly proportional to an average of the two input voltage signals. The cascode stage includes two parallel branches, each including an n-channel transistor connected in series with a p-channel transistor between the CMOS latch and ground. The bias signal is applied to the gate terminals of the n-channel transistors of both branches, and the two input voltages are respectively applied to the gate terminals of the p-channel transistors of the branches.Type: GrantFiled: September 18, 2001Date of Patent: September 10, 2002Assignee: Tower Semiconductor Ltd.Inventor: Oleg Dadashev
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Patent number: 6233180Abstract: A delay device for delaying the activation of a sensing indication signal includes a reference word-line, a reference word-line driver, and a comparator. The reference word-line driver is controlled by a strobe signal, and is connected to the reference word-line and a reference word-line voltage. Additionally, when so indicated by the strobe signal, the reference word-line driver provides the reference word-line voltage to the reference word-line. The comparator is connected to the reference word-line and to the reference word-line voltage and activates the sensing indication signal when the voltage on the reference word-line is at least equal to a predetermined function of the reference word-line voltage.Type: GrantFiled: February 4, 1999Date of Patent: May 15, 2001Assignees: Saifun Semiconductors Ltd., Tower Semiconductors Ltd.Inventors: Boaz Eitan, Oleg Dadashev
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Patent number: 6128226Abstract: A method for sensing a close to ground signal recieved from an array cell within a memory array includes the steps of providing a reference unit with a reference cell having a similar structure and a similar current path therethrough to that of the array cell, providing a timing unit with a timing cell having a similar structure and a similar current path therethrough to that of the array cell, discharging the array, the reference unit and the timing unit prior to charging them, generating a cell signal, a reference signal and a timing signal, respectively, upon charging, generating a read signal when the timing signal at least reaches a predefined voltage level and generating a sensing signal from the difference of the cell and reference signals once the read signal is generated. The reference unit has a reference capacitance which is a multiple of the expected capacitance of a bit line of the array and the timing unit has a predefined timing capacitance.Type: GrantFiled: February 4, 1999Date of Patent: October 3, 2000Assignees: Saifun Semiconductors Ltd., Tower Semiconductors Ltd.Inventors: Boaz Eitan, Oleg Dadashev
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Patent number: 6108240Abstract: A method and apparatus for erasing a single floating gate transistor in an array of floating gate transistors is provided. A selected floating gate transistor, which is located in a first row and a first column of the array, is erased as follows. A low voltage V.sub.LOW (e.g., 0 Volts) is applied to the gate of each transistor in the first row of the array. An erase voltage V.sub.ERASE (e.g., 8 Volts) is applied to the drain of each transistor in the first column of the array. An intermediate voltage V.sub.INT (e.g., 3 Volts) is applied to the source of each transistor in the array, as well as to the drain of each transistor of the array that is not in the first column. Under these conditions, only the selected floating gate transistor is erased. Other floating gate transistors in the first column are not erased because the gate-to-drain voltages of these transistors are limited by the intermediate voltage V.sub.INT applied to their gates.Type: GrantFiled: February 4, 1999Date of Patent: August 22, 2000Assignee: Tower Semiconductor Ltd.Inventors: Yoav Lavi, Oleg Dadashev
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Patent number: 6081456Abstract: A bit line control circuit for accessing an array of 2-bit non-volatile memory cells. Each memory cell has a first and a second charge trapping regions. A set of bit lines extends between the array and the bit line control circuit. The bit line control circuit includes pass transistors that selectively route pairs of bit lines to corresponding voltage control circuits in either a first order or a second (reversed) order. This enables both the first and second charge trapping regions of the memory cells to be accessed from the same voltage control circuits. In one embodiment, the bit line control circuit includes a first-level pass transistor coupled to each bit line. A second set of bit lines is coupled to the first-level pass transistors. A parallel-connected pair of second-level pass transistors is coupled to each bit line in the second set of bit lines. A third set of bit lines is coupled to the second-level pass transistors. The voltage control circuits are coupled to the third set of bit lines.Type: GrantFiled: February 4, 1999Date of Patent: June 27, 2000Assignee: Tower Semiconductor Ltd.Inventor: Oleg Dadashev