Patents by Inventor Oleg Kononchuk

Oleg Kononchuk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250210410
    Abstract: A method for transferring a thin film onto a support substrate comprises implanting into a donor substrate light species including co-implantation of hydrogen ions at a first dose and a first implantation energy, and helium ions at a second dose and a second implantation energy. Hydrogen ions are also locally implanted at a third dose and a third energy to form an overdosed local region in a buried fragile plane formed by the implanted ions. The donor substrate and the support substrate are assembled by direct bonding to form a bonded structure, and a fracture heat treatment is applied to the bonded structure so as to induce spontaneous separation along the buried fragile plane. The separation leads to the transfer of a thin film from the donor substrate onto the support substrate. The overdosed local region of the buried fragile plane constitutes a starting point for the separation.
    Type: Application
    Filed: March 20, 2023
    Publication date: June 26, 2025
    Inventors: Marianne Coig, Frédéric Mazen, Oleg Kononchuk, Didier Landru, Nadia Ben Mohamed
  • Publication number: 20250137928
    Abstract: A method and device for monitoring the weakening of an interface between a layer and a substrate while a weakening anneal is being carried out. The method includes illuminating the first face of the substrate layer assembly with a monochromatic light beam in a first direction; measuring the intensity of the light beam scattered by the substrate layer assembly in at least a second direction, the second direction forming a non-zero angle with the first direction; and determining a state of weakening of the interface from the intensity.
    Type: Application
    Filed: February 14, 2023
    Publication date: May 1, 2025
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Frédéric MAZEN, François RIEUTORD, Samuel TARDIF, Didier LANDRU, Oleg KONONCHUK, Nadia BEN MOHAMED
  • Publication number: 20250125140
    Abstract: A method of manufacturing a polycrystalline silicon carbide wafer includes the following stages: heat treatment of a polycrystalline silicon carbide slab; thinning of the polycrystalline silicon carbide slab, the thinning comprising a correction, by withdrawal of material from the polycrystalline silicon carbide slab, of a deformation brought about by the heat treatment.
    Type: Application
    Filed: January 27, 2023
    Publication date: April 17, 2025
    Inventors: Andrea Quintero-Colmenares, Frédéric Allibert, Alexis Drouin, Séverin Rouchier, Walter Schwarzenbach, Hugo Biard, Loïc Kabelaan, Oleg Kononchuk, Sidoine Odoul, Jérémy Roi
  • Publication number: 20250022747
    Abstract: A method for fabricating a structure comprises preparing a first pseudo-substrate, and in-depth weakening the first pseudo-substrate by ion implantation at a certain depth in the first pseudo-substrate. The first pseudo-substrate is prepared by providing a single crystal substrate comprising a piezoelectric material; forming an oxide layer on a surface of the single crystal substrate; and transferring a piezoelectric layer of the single crystal substrate adjacent the oxide layer to a handle substrate to form the first pseudo-substrate. The method further comprises bonding the first pseudo-substrate to a substrate to provide an assembly, and separating the assembly at the ion-implanted depth of the first pseudo-substrate to form the structure and a second pseudo-substrate. The structure comprises at least a portion of the piezoelectric layer of the single crystal substrate on the substrate.
    Type: Application
    Filed: September 30, 2024
    Publication date: January 16, 2025
    Inventors: Fabrice Letertre, Oleg Kononchuk
  • Patent number: 12198975
    Abstract: A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: January 14, 2025
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot
  • Publication number: 20240397825
    Abstract: The disclosure relates to a hybrid structure for a surface-acoustic-wave device comprising a useful layer of piezoelectric material joined to a carrier substrate having a thermal expansion coefficient lower than that of the useful layer; the hybrid structure comprising an intermediate layer located between the useful layer and the carrier substrate, the intermediate layer being a structured layer formed from at least two different materials comprising a plurality of periodic motifs in the plane of the intermediate layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Oleg Kononchuk, Eric Butaud, Eric Desbonnets
  • Publication number: 20240387243
    Abstract: A method for preparing a support substrate having a charge-trapping layer includes introducing a monocrystalline silicon base substrate into a chamber of deposition equipment and, without removing the base substrate from the chamber and while flushing the chamber with a carrier gas, performing the following successive steps: forming a dielectric layer on the base substrate by introducing a reactive gas into the chamber over a first time period; and forming a polycrystalline silicon charge-trapping layer directly on the dielectric layer by introducing a precursor gas containing silicon into the chamber over a second time period, subsequent to the first time period. The time for which the dielectric layer is exposed only to the carrier gas, between the first time period and the second time period, is less than 30 seconds and the formation of the charge-trapping layer is performed at a temperature strictly between 1010° C. and 1200° C.
    Type: Application
    Filed: October 19, 2022
    Publication date: November 21, 2024
    Inventors: Youngpil Kim, Oleg Kononchuk, Chee Hoe Wong
  • Patent number: 12142517
    Abstract: A method for transferring a useful layer from a donor substrate to a carrier substrate comprises: a) providing the donor substrate, the donor substrate including a buried weakened plane; b) providing the carrier substrate; c) joining the donor substrate to the carrier substrate to form a bonded structure; and d) annealing the bonded structure in order to increase the level of weakening of the buried weakened plane. A predetermined stress is applied to the buried weakened plane during the annealing for a period of time, the predetermined stress being selected so as to initiate the splitting wave once a given level of weakening has been reached. At the end of the period of time, the given level of weakening having been reached, the predetermined stress causes initiation and self-sustained propagation of the splitting wave along the buried weakened plane, resulting in the useful layer being transferred to the carrier substrate.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: November 12, 2024
    Assignee: Soitec
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: 12143093
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Grant
    Filed: July 14, 2023
    Date of Patent: November 12, 2024
    Assignee: Soitec
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk
  • Patent number: 12112976
    Abstract: The invention relates to a method for fabricating a pseudo-substrate comprising the steps of providing a single crystal ingot, providing a handle substrate, cutting a thin slice from the single crystal ingot, and attaching the thin slice to the handle substrate to form a pseudo-substrate. According to the invention, the thickness of the thin slice is substantially equal or inferior to a critical thickness below which the slice, if taken alone, is no longer mechanically stable. The invention further relates to a semiconductor structure.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: October 8, 2024
    Assignee: Soitec
    Inventors: Fabrice Letertre, Oleg Kononchuk
  • Patent number: 12108678
    Abstract: The disclosure relates to a hybrid structure for a surface-acoustic-wave device comprising a useful layer of piezoelectric material joined to a carrier substrate having a thermal expansion coefficient lower than that of the useful layer; the hybrid structure comprising an intermediate layer located between the useful layer and the carrier substrate, the intermediate layer being a structured layer formed from at least two different materials comprising a plurality of periodic motifs in the plane of the intermediate layer.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: October 1, 2024
    Assignee: SOITEC
    Inventors: Oleg Kononchuk, Eric Butaud, Eric Desbonnets
  • Publication number: 20240266172
    Abstract: The invention relates to a semiconductor structure (100) that comprises a useful layer (10) made of monocrystalline semiconductor material and extending along a main plane (x, y), a support substrate (30) made of semiconductor material, and an interface area (20) between the useful layer (10) and the support substrate (30), the support substrate extending parallel to the main plane (x, y), the structure (100) being characterised in that the interface area (20) comprises nodules (21) that:—are electrically conductive, in that they contain a metal material forming ohmic contact with the useful layer (10) and the support substrate (30);—have a thickness, along an axis (z) normal to the main plane (x, y) , of less than or equal to 30 nm;—are separate or adjoining, the separate nodules (21) being separated from each other by regions (22) of direct contact between the useful layer (10) and the support substrate (30). The invention also relates to a method for manufacturing the structure (100).
    Type: Application
    Filed: June 8, 2021
    Publication date: August 8, 2024
    Inventors: Frédéric Allibert, Didier Landru, Oleg Kononchuk, Eric Guiot, Gweltaz Gaudin, Julie Widiez, Franck Fournel
  • Publication number: 20240222158
    Abstract: A system for fracturing a plurality of wafer assemblies, one of the wafers of each assembly comprising a plane of weakness and each assembly comprising a peripheral lateral groove comprises: a cradle for keeping the assemblies of the plurality of assemblies spaced apart and parallel to one another, along a storage axis; a separation device for applying separating forces in the peripheral groove of an assembly arranged in a fracture zone of the separating device, the separating force aiming to separate the wafers of the assembly from one another so as to initiate its fracture at the plane of weakness; and a drive device configured to move along the storage axis of the cradle opposite the separating device so as to successively place an assembly of the cradle in the fracture zone of the separation device.
    Type: Application
    Filed: March 18, 2024
    Publication date: July 4, 2024
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: 12002697
    Abstract: A method for monitoring a heat treatment applied to a substrate comprising a weakened zone formed by implanting atomic species for splitting the substrate along the weakened zone, the substrate being arranged in a heating chamber, the method comprising recording sound in the interior or in the vicinity of the heating chamber and detecting, in the recording, a sound emitted by the substrate during the splitting thereof along the weakened zone. A device for the heat treatment of a batch of substrates comprises an annealing furnace comprising a heating chamber intended to receive the batch, at least one microphone configured to record sounds in the interior or in the vicinity of the heating chamber, and a processing system configured to detect, in an audio recording produced by the microphone, a sound emitted when a substrate splits.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: June 4, 2024
    Assignee: Soitec
    Inventors: François Rieutord, Frédéric Mazen, Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: 12002690
    Abstract: A system for fracturing a plurality of wafer assemblies, one of the wafers of each assembly comprising a plane of weakness and each assembly comprising a peripheral lateral groove comprises: a cradle for keeping the assemblies of the plurality of assemblies spaced apart and parallel to one another, along a storage axis; a separation device for applying separating forces in the peripheral groove of an assembly arranged in a fracture zone of the separating device, the separating force aiming to separate the wafers of the assembly from one another so as to initiate its fracture at the plane of weakness; and a drive device configured to move along the storage axis of the cradle opposite the separating device so as to successively place an assembly of the cradle in the fracture zone of the separation device.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 4, 2024
    Assignee: SOITEC
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: 11923239
    Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: March 5, 2024
    Assignee: Soitec
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Publication number: 20240071755
    Abstract: A support substrate for a radiofrequency application comprises: —a base substrate made of monocrystalline silicon comprising P-type dopants and having a resistivity that is greater than or equal to 250 ohm·cm and strictly less than 500 ohm·cm, and a content of interstitial oxygen between 13 ppma and 19 ppma, —an epitaxial layer made of monocrystalline silicon comprising P-type dopants, disposed on the base substrate and having a thickness between 2 microns and 30 microns, an upper portion at least of the epitaxial layer having a resistivity greater than 3000 ohm·cm, —a charge-trapping layer made of polycrystalline silicon having a resistivity greater than or equal to 1000 ohm·cm and a thickness between 1 micron and 10 microns. A method is used for manufacturing such a support substrate.
    Type: Application
    Filed: December 23, 2021
    Publication date: February 29, 2024
    Inventors: Oleg Kononchuk, Christophe Maleville, Isabelle Bertrand, Youngpil Kim, Chee Hoe Wong
  • Publication number: 20240030060
    Abstract: A method for preparing a thin layer comprises a weakening step for forming a weakened zone in a central portion of a donor substrate, the weakened zone not extending into a peripheral portion of the donor substrate; a step of joining the main face of the donor substrate to a receiver substrate to form an assembly to be split; and a step of separating the assembly to be split, the separating step comprising a heat treatment resulting in the freeing of the thin layer from the donor substrate at the central portion thereof only. The method also comprises, after the separating step, a detaching step comprising the treating of the assembly to be split in order to detach the peripheral portion of the donor substrate from the receiver substrate.
    Type: Application
    Filed: January 19, 2021
    Publication date: January 25, 2024
    Inventors: Frédéric Mazen, François Rieutord, Marianne Coig, Helen Grampeix, Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: 11881429
    Abstract: A method for transferring a useful layer to a carrier substrate, includes the following steps: a) providing a donor substrate including a buried weakened plane; b) providing a carrier substrate; c) joining the donor substrate, by its front face, to the carrier substrate along a bonding interface so as to form a bonded structure; d) annealing the bonded structure in order to apply a weakening thermal budget thereto and to bring the buried weakened plane to a defined level of weakening; and e) initiating a splitting wave in the weakened plane by applying a stress to the bonded structure, the splitting wave self-propagating along the weakened plane to result in the useful layer being transferred to the carrier substrate. The splitting wave is initiated when the bonded structure is subjected to a temperature between 150° C. and 250° C.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: January 23, 2024
    Assignee: SOITEC
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: 11876015
    Abstract: A method for transferring a useful layer to a carrier substrate comprises: joining a front face of a donor substrate to a carrier substrate along a bonding interface to form a bonded structure; annealing the bonded structure to apply a weakening thermal budget thereto and bring a buried weakened plane in the donor substrate to a defined level of weakening, the anneal reaching a maximum hold temperature; and initiating a self-sustained and propagating splitting wave in the buried weakened plane by applying a stress to the bonded structure to lead to the useful layer being transferred to the carrier substrate. The initiation of the splitting wave occurs when the bonded structure experiences a thermal gradient defining a hot region and a cool region of the bonded structure, the stress being applied locally in the cool region, and the hot region experiencing a temperature lower than the maximum hold temperature.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: January 16, 2024
    Assignee: Soitec
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed, Franck Colas