Patents by Inventor Oleg Kononchuk

Oleg Kononchuk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11923239
    Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: March 5, 2024
    Assignee: Soitec
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Publication number: 20240071755
    Abstract: A support substrate for a radiofrequency application comprises: —a base substrate made of monocrystalline silicon comprising P-type dopants and having a resistivity that is greater than or equal to 250 ohm·cm and strictly less than 500 ohm·cm, and a content of interstitial oxygen between 13 ppma and 19 ppma, —an epitaxial layer made of monocrystalline silicon comprising P-type dopants, disposed on the base substrate and having a thickness between 2 microns and 30 microns, an upper portion at least of the epitaxial layer having a resistivity greater than 3000 ohm·cm, —a charge-trapping layer made of polycrystalline silicon having a resistivity greater than or equal to 1000 ohm·cm and a thickness between 1 micron and 10 microns. A method is used for manufacturing such a support substrate.
    Type: Application
    Filed: December 23, 2021
    Publication date: February 29, 2024
    Inventors: Oleg Kononchuk, Christophe Maleville, Isabelle Bertrand, Youngpil Kim, Chee Hoe Wong
  • Publication number: 20240030060
    Abstract: A method for preparing a thin layer comprises a weakening step for forming a weakened zone in a central portion of a donor substrate, the weakened zone not extending into a peripheral portion of the donor substrate; a step of joining the main face of the donor substrate to a receiver substrate to form an assembly to be split; and a step of separating the assembly to be split, the separating step comprising a heat treatment resulting in the freeing of the thin layer from the donor substrate at the central portion thereof only. The method also comprises, after the separating step, a detaching step comprising the treating of the assembly to be split in order to detach the peripheral portion of the donor substrate from the receiver substrate.
    Type: Application
    Filed: January 19, 2021
    Publication date: January 25, 2024
    Inventors: Frédéric Mazen, François Rieutord, Marianne Coig, Helen Grampeix, Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: 11881429
    Abstract: A method for transferring a useful layer to a carrier substrate, includes the following steps: a) providing a donor substrate including a buried weakened plane; b) providing a carrier substrate; c) joining the donor substrate, by its front face, to the carrier substrate along a bonding interface so as to form a bonded structure; d) annealing the bonded structure in order to apply a weakening thermal budget thereto and to bring the buried weakened plane to a defined level of weakening; and e) initiating a splitting wave in the weakened plane by applying a stress to the bonded structure, the splitting wave self-propagating along the weakened plane to result in the useful layer being transferred to the carrier substrate. The splitting wave is initiated when the bonded structure is subjected to a temperature between 150° C. and 250° C.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: January 23, 2024
    Assignee: SOITEC
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: 11876015
    Abstract: A method for transferring a useful layer to a carrier substrate comprises: joining a front face of a donor substrate to a carrier substrate along a bonding interface to form a bonded structure; annealing the bonded structure to apply a weakening thermal budget thereto and bring a buried weakened plane in the donor substrate to a defined level of weakening, the anneal reaching a maximum hold temperature; and initiating a self-sustained and propagating splitting wave in the buried weakened plane by applying a stress to the bonded structure to lead to the useful layer being transferred to the carrier substrate. The initiation of the splitting wave occurs when the bonded structure experiences a thermal gradient defining a hot region and a cool region of the bonded structure, the stress being applied locally in the cool region, and the hot region experiencing a temperature lower than the maximum hold temperature.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: January 16, 2024
    Assignee: Soitec
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed, Franck Colas
  • Patent number: 11855120
    Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 ?m is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: December 26, 2023
    Assignee: SOITEC
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot, Christelle Michau
  • Publication number: 20230378931
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 23, 2023
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk
  • Publication number: 20230291377
    Abstract: A process for manufacturing a piezoelectric structure for a radiofrequency device comprises providing a substrate of piezoelectric material, providing a carrier substrate, providing a dielectric bonding layer on the substrate of piezoelectric material, a step of joining the substrate of piezoelectric material to the carrier substrate via the dielectric bonding layer, and a thinning step for forming the piezoelectric structure, which comprises a layer of piezoelectric material joined to a carrier substrate via the dielectric bonding layer.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 14, 2023
    Inventors: Djamel Belhachemi, Thierry Barge, Oleg Kononchuk, Brice Tavel
  • Publication number: 20230238274
    Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RE devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.
    Type: Application
    Filed: March 29, 2023
    Publication date: July 27, 2023
    Inventors: Arnaud Castex, Oleg Kononchuk
  • Patent number: 11711065
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: July 25, 2023
    Assignee: Soitec
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk
  • Patent number: 11670540
    Abstract: Substrates may include a useful layer affixed to a support substrate. A surface of the useful layer located on a side of the useful layer opposite the support substrate may include a first region and a second region. The first region may have a first surface roughness, may be located proximate to a geometric center of the surface, and may occupy a majority of an area of the surface. The second region may have a second, higher surface roughness, may be located proximate to a periphery of the surface, and may occupy a minority of the area of the surface.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: June 6, 2023
    Assignees: Soitec, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Didier Landru, Nadia Ben Mohamed, Oleg Kononchuk, Frédéric Mazen, Damien Massy, Shay Reboh, François Rieutord
  • Patent number: 11626319
    Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: April 11, 2023
    Assignee: Soitec
    Inventors: Arnaud Castex, Oleg Kononchuk
  • Publication number: 20220319910
    Abstract: A process for hydrophilic bonding first and second substrates, comprising: —bringing the first and second substrates into contact to form a bonding interface between main surfaces of the first and second substrates, and —applying a heat treatment to close the bonding interface. The process further comprises, before the step of bringing into contact, depositing, on the main surface of the first and/or second substrate, a bonding layer comprising a non-metallic material that is permeable to dihydrogen and that has, at the temperature of the heat treatment, a yield strength lower than that of at least one of the materials of the first substrate and of the second substrate located at the bonding interface. The layer has a thickness between 1 and 6 nm, and the heat treatment is carried out at a temperature lower than or equal to 900° C., and preferably lower than or equal to 600° C.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 6, 2022
    Inventors: Vincent Larrey, François Rieutord, Jean-Michel Hartmann, Frank Fournel, Didier Landru, Oleg Kononchuk, Ludovic Ecarnot
  • Publication number: 20220277988
    Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Patent number: 11424156
    Abstract: A detachable structure comprises a carrier substrate and a silicon oxide layer positioned on the substrate at a first interface. The detachable structure is notable in that: the oxide layer has a thickness of less than 200 nm; light hydrogen and/or helium species are distributed deeply and over the entire area of the structure according to an implantation profile, a maximum concentration of which is located in the thickness of the oxide layer; the total dose of implanted light species, relative to the thickness of the oxide layer, exceeds, at least by a factor of five, the solubility limit of these light species in the oxide layer.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: August 23, 2022
    Assignee: Soitec
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed, Rénald Guerin, Norbert Colombet
  • Patent number: 11367650
    Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: June 21, 2022
    Assignee: Soitec
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Publication number: 20220181173
    Abstract: A system for fracturing a plurality of wafer assemblies, one of the wafers of each assembly comprising a plane of weakness and each assembly comprising a peripheral lateral groove comprises: a cradle for keeping the assemblies of the plurality of assemblies spaced apart and parallel to one another, along a storage axis; a separation device for applying separating forces in the peripheral groove of an assembly arranged in a fracture zone of the separating device, the separating force aiming to separate the wafers of the assembly from one another so as to initiate its fracture at the plane of weakness; and a drive device configured to move along the storage axis of the cradle opposite the separating device so as to successively place an assembly of the cradle in the fracture zone of the separation device.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 9, 2022
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Publication number: 20220172983
    Abstract: A method for transferring a useful layer from a donor substrate to a carrier substrate comprises: a) providing the donor substrate, the donor substrate including a buried weakened plane; b) providing the carrier substrate; c) joining the donor substrate to the carrier substrate to form a bonded structure; and d) annealing the bonded structure in order to increase the level of weakening of the buried weakened plane. A predetermined stress is applied to the buried weakened plane during the annealing for a period of time, the predetermined stress being selected so as to initiate the splitting wave once a given level of weakening has been reached. At the end of the period of time, the given level of weakening having been reached, the predetermined stress causes initiation and self-sustained propagation of the splitting wave along the buried weakened plane, resulting in the useful layer being transferred to the carrier substrate.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 2, 2022
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Publication number: 20220157651
    Abstract: A method for transferring a useful layer to a carrier substrate, includes the following steps: a) providing a donor substrate including a buried weakened plane; b) providing a carrier substrate; c) joining the donor substrate, by its front face, to the carrier substrate along a bonding interface so as to form a bonded structure; d) annealing the bonded structure in order to apply a weakening thermal budget thereto and to bring the buried weakened plane to a defined level of weakening; and e) initiating a splitting wave in the weakened plane by applying a stress to the bonded structure, the splitting wave self-propagating along the weakened plane to result in the useful layer being transferred to the carrier substrate. The splitting wave is initiated when the bonded structure is subjected to a temperature between 150° C. and 250° C.
    Type: Application
    Filed: February 26, 2020
    Publication date: May 19, 2022
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: RE49365
    Abstract: A structure for radiofrequency applications includes: a support substrate of high-resistivity silicon comprising a lower part and an upper part having undergone a p-type doping to a depth D; a mesoporous trapping layer of silicon formed in the doped upper part of the support substrate. The depth D is less than 1 micron and the trapping layer has a porosity rate of between 20% and 60%.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: January 10, 2023
    Assignee: Soitec
    Inventors: Oleg Kononchuk, William Van Den Daele, Eric Desbonnets