Patents by Inventor Oleg Kononchuk

Oleg Kononchuk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210050249
    Abstract: A detachable structure comprises a carrier substrate and a silicon oxide layer positioned on the substrate at a first interface. The detachable structure is notable in that: the oxide layer has a thickness of less than 200 nm; light hydrogen and/or helium species are distributed deeply and over the entire area of the structure according to an implantation profile, a maximum concentration of which is located in the thickness of the oxide layer; the total dose of implanted light species, relative to the thickness of the oxide layer, exceeds, at least by a factor of five, the solubility limit of these light species in the oxide layer.
    Type: Application
    Filed: January 14, 2019
    Publication date: February 18, 2021
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed, Rénald Guerin, Norbert Colombet
  • Publication number: 20210050248
    Abstract: The invention relates to a method for fabricating a pseudo-substrate comprising the steps of providing a single crystal ingot, providing a handle substrate, cutting a thin slice from the single crystal ingot, and attaching the thin slice to the handle substrate to form a pseudo-substrate. According to the invention, the thickness of the thin slice is substantially equal or inferior to a critical thickness below which the slice, if taken alone, is no longer mechanically stable. The invention further relates to a semiconductor structure.
    Type: Application
    Filed: November 3, 2020
    Publication date: February 18, 2021
    Inventors: Fabrice Letertre, Oleg Kononchuk
  • Patent number: 10924081
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: February 16, 2021
    Assignee: Soitec
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk
  • Patent number: 10910256
    Abstract: The invention relates to a method for fabricating a pseudo-substrate comprising the steps of providing a single crystal ingot, providing a handle substrate, cutting a thin slice from the single crystal ingot, and attaching the thin slice to the handle substrate to form a pseudo-substrate. According to the invention, the thickness of the thin slice is substantially equal or inferior to a critical thickness below which the slice, if taken alone, is no longer mechanically stable. The invention further relates to a semiconductor structure.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 2, 2021
    Assignee: Soitec
    Inventors: Fabrice Letertre, Oleg Kononchuk
  • Publication number: 20210028036
    Abstract: A method for monitoring a heat treatment applied to a substrate comprising a weakened zone formed by implanting atomic species for splitting the substrate along the weakened zone, the substrate being arranged in a heating chamber, the method comprising recording sound in the interior or in the vicinity of the heating chamber and detecting, in the recording, a sound emitted by the substrate during the splitting thereof along the weakened zone. A device for the heat treatment of a batch of substrates comprises an annealing furnace comprising a heating chamber intended to receive the batch, at least one microphone configured to record sounds in the interior or in the vicinity of the heating chamber, and a processing system configured to detect, in an audio recording produced by the microphone, a sound emitted when a substrate splits.
    Type: Application
    Filed: March 22, 2019
    Publication date: January 28, 2021
    Inventors: François Rieutord, Frédéric Mazen, Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: 10886162
    Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 5, 2021
    Assignee: Soitec
    Inventors: Arnaud Castex, Oleg Kononchuk
  • Publication number: 20200228088
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 16, 2020
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk
  • Publication number: 20200152689
    Abstract: A semiconductor on insulator type structure, which may be sued for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.
    Type: Application
    Filed: March 21, 2018
    Publication date: May 14, 2020
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot
  • Publication number: 20200127041
    Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and/or metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 ?m is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.
    Type: Application
    Filed: January 10, 2018
    Publication date: April 23, 2020
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot, Christelle Michau
  • Patent number: 10619997
    Abstract: A method for measuring thickness variations in a first layer of a semiconductor structure includes: acquiring an image of at least one zone of the surface of the structure, processing the acquired image so as to determine a map of the thickness variations of the first layer, and comparing the intensity of each pixel of the image with a predetermined calibration curve, the calibration curve being determined for a given thickness of a second layer of the structure, and measuring the thickness of the second layer in the at least one zone, -if the measured thickness is different from the thickness of the second layer considered in the calibration curve, using a correction curve to determine a corrected map of thickness variations of the first layer.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: April 14, 2020
    Assignee: Soitec
    Inventor: Oleg Kononchuk
  • Patent number: 10608610
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: March 31, 2020
    Assignee: Soitec
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk
  • Publication number: 20200054978
    Abstract: A vertical furnace includes a chamber intended for receiving a loading column an inlet channel for fresh gas, arranged at an upper end of the chamber, the loading column comprising an upper portion, and a central portion for supporting a plurality of substrates. The vertical furnace further comprises a trapping device made of at least one material suitable for trapping all or part of the contaminants present in the fresh gas. The trapping device includes a circular part arranged on the upper part of the loading column, the circular part comprising fins regularly distributed over an upper surface of the circular part in order to increase the contact surface of the trapping device with the fresh gas.
    Type: Application
    Filed: September 21, 2017
    Publication date: February 20, 2020
    Inventors: Didier Landru, Oleg Kononchuk
  • Patent number: 10510565
    Abstract: A thermal treatment system includes a chamber capable of receiving a plurality of substrates, a gas intake path in a distal portion of the chamber located opposite an area for entry of substrates into the chamber, and an outlet path for the gas and/or volatile species generated during the thermal treatment. The outlet path is located in a proximal portion of the chamber located near the area for entry of the substrates into the chamber. The system further includes a collector device in the proximal portion of the chamber. The collector device has a confinement opening oriented toward the distal portion of the chamber, and the collector device defines a compartment communicating with the outlet path, the compartment being configured so that the gas and the volatile species enter into the compartment via the confinement opening and pass through the compartment to reach the outlet path.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: December 17, 2019
    Assignee: Soitec
    Inventors: Didier Landru, Oleg Kononchuk, Sébastien Simon
  • Patent number: 10510531
    Abstract: A method of fabrication of a semiconductor element includes a step of rapid heat treatment in which a substrate comprising a base having a resistivity greater than 1000 Ohm·cm is exposed to a peak temperature sufficient to deteriorate the resistivity of the base. The step of rapid heat treatment is followed by a curing heat treatment in which the substrate is exposed to a curing temperature between 800° C. and 1250° C. and then cooled at a cooldown rate less than 5° C./second when the curing temperature is between 1250° C. and 1150° C., less than 20° C./second when the curing temperature is between 1150° C. and 1100° C., and less than 50° C./second when the curing temperature is between 1100° C. and 800° C.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: December 17, 2019
    Assignee: Soitec
    Inventors: Oleg Kononchuk, Isabelle Bertrand, Luciana Capello, Marcel Broekaart
  • Publication number: 20190348462
    Abstract: A substrate for a front-side-type image sensor includes, successively, a supporting semiconductor substrate, an electrically insulating layer, and a semiconductor layer, known as the active layer. The active layer is an epitaxial layer of silicon-germanium having a germanium content of less than 10%. The disclosure also relates to a method for the production of such a substrate.
    Type: Application
    Filed: January 10, 2018
    Publication date: November 14, 2019
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot, Christelle Michau
  • Publication number: 20190348319
    Abstract: A method of fabricating a semiconductor substrate includes the following activities: a) providing a donor substrate with a weakened zone inside the donor substrate, the weakened zone forming a border between a layer to be transferred and the rest of the donor substrate, b) attaching the donor substrate to a receiver substrate, the layer to be transferred being located at the interface between the donor substrate and the receiver substrate; c) detaching the receiver substrate along with the transferred layer from the rest of the donor substrate, at the weakened zone; and d) at least one step of smoothing the surface of the transferred layer, wherein the semiconductor substrate obtained from step c) is kept, at least from the moment of detachment until the end of the smoothing step, in a non-oxidizing inert atmosphere or in a mixture of non-oxidizing inert gases.
    Type: Application
    Filed: January 10, 2018
    Publication date: November 14, 2019
    Inventors: Oleg Kononchuk, Didier Landru, Nadia Ben Mohamed
  • Publication number: 20190228967
    Abstract: A structure that can be used to manufacture at least one active layer made of a III-V material thereon includes a substrate comprising a carrier having a main face, a dielectric layer located on the main face of the carrier, and a plurality of single-crystal semiconductor islands located directly on the dielectric layer. The islands have an upper surface in order to serve as a seed surface for the growth of the active layer. The structure further comprises a seed layer located between the single-crystal semiconductor islands, directly on the portion of the dielectric layer that is not covered by the islands, without masking the upper surface of the islands, so that the dielectric layer is not exposed to the external environment.
    Type: Application
    Filed: September 21, 2017
    Publication date: July 25, 2019
    Inventors: David Sotta, Jean-Marc Bethoux, Oleg Kononchuk
  • Publication number: 20190221471
    Abstract: A useful layer is layered onto a support by a method that includes the steps of forming an embrittlement plane by implanting light elements into a first substrate, so as to form a useful layer between such plane and one surface of the first substrate; applying the support onto the surface of the first substrate so as to form an assembly to be fractured; applying a heat treatment for embrittling the assembly to be fractured; and initiating and propagating a fracture wave into the first substrate along the embrittlement plane. The fracture wave is initiated in a central area of the embrittlement plane and the propagation speed of the wave is controlled so that the velocity thereof is sufficient to cause the interactions of the fracture wave with acoustic vibrations emitted upon the initiation and/or propagation thereof, if any, are confined to a peripheral area of the useful layer.
    Type: Application
    Filed: August 1, 2017
    Publication date: July 18, 2019
    Applicants: Commissariat A L'Energie Atomique et aux Energies Alternatives, Soitec, Soitec
    Inventors: Didier Landru, Nadia Ben Mohamed, Oleg Kononchuk, Frederic Mazen, Damien Massy, Shay Reboh, Francois Rieutord
  • Patent number: 10347597
    Abstract: A structure for radiofrequency applications includes: a support substrate of high-resistivity silicon comprising a lower part and an upper part having undergone a p-type doping to a depth D; a mesoporous trapping layer of silicon formed in the doped upper part of the support substrate. The depth D is less than 1 micron and the trapping layer has a porosity rate of between 20% and 60%.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: July 9, 2019
    Assignee: Soitec
    Inventors: Oleg Kononchuk, William Van Den Daele, Eric Desbonnets
  • Publication number: 20190157137
    Abstract: A substrate for microelectronic radiofrequency devices includes a carrier substrate made of a first semiconductor material having a resistivity higher than 500 ohms·cm; a plurality of trenches in the carrier substrate, which trenches are filled with a second material, and defining on a first side of the carrier substrate a plurality of first zones made of a first material and at least one second zone made of a second material. The second material has a resistivity higher than 10 kohms·cm, and the first zones have a maximum dimension smaller than 10 microns and are insulated from one another by the second zone.
    Type: Application
    Filed: June 6, 2017
    Publication date: May 23, 2019
    Applicant: Soitec
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin