Abstract: In an embodiment, an electronic device includes a semiconductor layer having a surface, a gate and a first current electrode on the surface and a dielectric layer extending between the gate and the first current electrode and including charged ions having a predetermined charge profile.

Abstract: A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.

Abstract: A semiconductor device is provided that includes a transistor in a semiconductor body having a main surface. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The body region and the drift zone are disposed along a first direction between the source region and the drain region. The first direction is parallel to the main surface. The semiconductor device further includes a field plate disposed in field plate trenches extending along the first direction in the drift zone, and a field dielectric layer between the field plate and the drift zone. A thickness of the field dielectric layer gradually increases along the first direction from a portion adjacent to the source region to a portion adjacent to the drain region.

Abstract: A semiconductor component includes a semiconductor chip including a first semiconductor body comprising silicon and a second semiconductor body attached to an upper side of the first semiconductor body and comprising a III-nitride, and a lead-frame connected with the first semiconductor body. A thickness ratio between a thickness of the semiconductor chip and a thickness of the lead-frame is smaller than 1.3 or larger than 1.9.

Abstract: A method of manufacturing an electronic component includes applying solder paste to at least one electrically conductive portion of a package, applying a high-voltage depletion-mode transistor onto the solder paste, applying a low-voltage enhancement-mode transistor onto the solder paste, applying solder paste onto the high-voltage depletion-mode transistor, applying solder paste onto the low-voltage enhancement-mode transistor, applying an electrically conductive member onto the solder paste on the high-voltage depletion-mode transistor and onto the solder paste on the low-voltage enhancement-mode transistor to form an assembly, and heat treating the assembly to produce an electrical connection between the high-voltage depletion-mode transistor and the low-voltage enhancement-mode transistor via the electrically conductive member.

Abstract: A substrate having a buffer layer and a barrier layer is formed. The buffer and barrier layers have different bandgaps such that an electrically conductive channel comprising a two-dimensional charge carrier gas arises at an interface between the buffer and barrier layers due to piezoelectric effects. The substrate is placed in a fluorine containing gas mixture that includes free radical state fluorine particles and is substantially devoid of ionic state fluorine particles. A first lateral surface section of the substrate is exposed to the gas mixture such that the free radical state fluorine particles contact the first lateral surface section without penetrating the substrate. A semiconductor device that incorporates first lateral surface section in the structure of the device is formed in the substrate.

Abstract: An electronic circuit includes a transistor arrangement with a plurality of transistor devices, each including a control node and a load path between a first load node and a second load node, and having the load paths connected in parallel. The electronic circuit further includes a drive circuit coupled to the control node of each of the plurality of transistor devices, and configured to receive an input signal. Each of the plurality of transistor devices includes a two-dimensional electron gas (2DEG) in the load path, and a field plate adjacent the 2DEG. The drive circuit is configured to receive a load signal that represents at least one load parameter of the transistor arrangement and is configured to one of activate and deactivate at least one of the plurality of transistor devices based on the load signal.

Abstract: A semiconductor component may include a semiconductor layer which has a front side and a back side, a first terminal electrode on the front side, a second terminal electrode on the back side, a first dopant region of a first conduction type on the front side, which is electrically connected to one of the terminal electrodes, a second dopant region of a second conduction type in the semiconductor layer, which is electrically connected to the other terminal electrode, a pn junction being formed between the first and second dopant regions, a dielectric layer on the back side between the semiconductor layer and the second terminal electrode, and the dielectric layer having an opening through which an electrical connection between the second terminal electrode and the first or second dopant region is passed.

Abstract: An electronic component includes a high-voltage depletion-mode transistor, a low-voltage enhancement-mode transistor arranged adjacent and spaced apart from the high-voltage depletion-mode transistor, and an electrically conductive member electrically coupling a first current electrode of the high-voltage depletion-mode transistor to a first current electrode of the low-voltage enhancement-mode transistor. The electrically conductive member has a sheet-like form.

Abstract: A transistor device includes a compound semiconductor body having a first surface and a two-dimensional charge carrier gas disposed below the first surface in the compound semiconductor body. The transistor device further includes a source in contact with the two-dimensional charge carrier gas and a drain spaced apart from the source and in contact with the two-dimensional charge carrier gas. A first passivation layer is in contact with the first surface of the compound semiconductor body, and a second passivation layer is disposed on the first passivation layer. The second passivation layer has a different etch rate selectivity than the first passivation layer. A gate extends through the second passivation layer into the first passivation layer.

Abstract: A substrate having a buffer layer and a barrier layer is formed. The buffer and barrier layers have different bandgaps such that an electrically conductive channel comprising a two-dimensional charge carrier gas arises at an interface between the buffer and barrier layers due to piezoelectric effects. The substrate is placed in a fluorine containing gas mixture that includes free radical state fluorine particles and is substantially devoid of ionic state fluorine particles. A first lateral surface section of the substrate is exposed to the gas mixture such that the free radical state fluorine particles contact the first lateral surface section without penetrating the substrate. A semiconductor device that incorporates first lateral surface section in the structure of the device is formed in the substrate.

Abstract: A semiconductor disk of a first crystalline material, which has a first lattice system, is bonded on a process surface of a base substrate, wherein a bonding layer is formed between the semiconductor disk and the base substrate. A second semiconductor layer of a second crystalline material with a second, different lattice system is formed by epitaxy on a first semiconductor layer formed from the semiconductor disk.

Abstract: A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a first p-type Group III-nitride layer, and a second side face of the multi-heterojunction fin structure is covered by a second p-type Group III-nitride layer.

Abstract: In an embodiment, a switching circuit includes a high voltage depletion mode transistor having a first leakage current and operatively connected in a cascode arrangement to a low voltage enhancement mode transistor having a second leakage current. The second leakage current is larger than the first leakage current.

Abstract: In an embodiment, a semiconductor device includes a substrate, a Group III nitride-based semiconductor layer formed on the substrate, a first current electrode and a second current electrode formed on the Group III nitride-based semiconductor layer and spaced from each other, and a control electrode formed on the Group III nitride-based semiconductor layer between the first current electrode and the second current electrode. The control electrode includes at least a middle portion, configured to switch off a channel below the middle portion when a first voltage is applied to the control electrode, and second portions adjoining the middle portion. The second portions are configured to switch off a channel below the second portions when a second voltage is applied to the control electrode, the second voltage being less than the first voltage and the second voltage being less than a threshold voltage of the second portions.

Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.

Abstract: A method of manufacturing a transistor device includes forming a compound semiconductor material on a semiconductor carrier, forming a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions, forming a Schottky diode integrated with the semiconductor carrier, and forming contacts extending from the source and drain regions through the compound semiconductor material and in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions.

Abstract: One aspect relates to a semiconductor component with a semiconductor body, a first main contact pad, a second main contact pad, a normally-on first transistor monolithically integrated in the semiconductor body and a normally-off second transistor monolithically integrated in the semiconductor body. The first transistor is a high electron mobility transistor having a first gate electrode and a first load path controllable via a first gate electrode, and the second transistor has a second gate electrode and a second load path controllable via the second gate electrode. The first load path and the second load path are electrically connected in series between the first main contact pad and the second main contact pad.

Abstract: A semiconductor device includes a first compound semiconductor material and a second compound semiconductor material on the first compound semiconductor material. The second compound semiconductor material comprises a different material than the first compound semiconductor material such that the first compound semiconductor material has a two-dimensional electron gas (2DEG). The semiconductor device further includes a buried field plate disposed in the first compound semiconductor material and electrically connected to a terminal of the semiconductor device. The 2DEG is interposed between the buried field plate and the second compound semiconductor material.

Abstract: A normally-off transistor includes a first region of III-V semiconductor material, a second region of III-V semiconductor material on the first region, a third region of III-V semiconductor material on the second region and a gate electrode adjacent at least one sidewall of the third region. The first region provides a channel of the transistor. The second region has a band gap greater than the band gap of the first region and causes a 2-D electron gas (2DEG) in the channel. The second region is interposed between the first region and the third region. The third region provides a gate of the transistor and has a thickness sufficient to deplete the 2DEG in the channel so that the transistor has a positive threshold voltage.