Abstract: In a microprocessor configuration, data is temporarily stored in a cache memory or a register bank. A respectively assigned cryptographic unit ensures that the data is encrypted or decrypted when the cache memory or the register bank is accessed. The keyword which is used here is changed if the cache memory or the register no longer contains any valid data to be read out. As a result, an increased protection is obtained against unauthorized monitoring of data and program sequences.

Abstract: A data processing method and system including a processor, a user data storage medium, and a management data storage medium, wherein the management data are used to manage the user data.

Abstract: A heat pump comprises an evaporator for evaporating water as a working liquid so as to produce a working vapor, the evaporation taking place at an evaporation pressure of less than 20 hPa. The working vapor is compressed to a working pressure of at least 25 hPa by a dynamic-type compressor so as to then be liquefied within a liquefier by direct contact with liquefier water. The heat pump is preferably an open system, wherein water present in the environment in the form of ground water, sea water, river water, lake water or brine is evaporated, and wherein water which has been liquefied again is fed to the evaporator, to the soil or to a water treatment plant.

Abstract: A microcontroller for security applications includes an encryption unit between a bus and a functional unit. The encryption unit includes a gate and a key register. A memory is provided with a further encryption unit whose gate is connected between the register and the gate of the first encryption unit. As a result, the transferred information item is available in encrypted form at any point on the bus.

Abstract: A data-processing apparatus has a data provider for providing an input datum encrypted by an encryption key. In addition, the data-processing apparatus has a key stream generator for generating a key stream in a predetermined deterministic manner such that the key stream has a decryption key corresponding to the encryption key. Furthermore, the data-processing apparatus has a data processor for processing the encrypted input datum in a masked manner using the decryption key as a temporary key to obtain an output datum encrypted by an output key such that the encrypted output datum corresponds to a result, encrypted by the output key, of a predetermined operation on the encrypted input datum having been decrypted by the decryption key.

Abstract: A data processing apparatus comprises a data processing module, which can be operated in a first operating mode with a normal power consumption and a second operating mode, wherein a power consumption of the data processing module in the second operating mode is smaller than the first power consumption or equal to 0. The data processing apparatus further comprises means for signaling a possibility that the data processing module can be placed into the second operating mode, means for providing a time-varying control signal, means for placing the data processing module from one data operating mode to the other, wherein means for placing is formed to place the data processing module into the other operating mode, when means for signaling signals the possibility and the control signal fulfills a predetermined condition.

Abstract: A shift device for shifting a first place of a data word, which consists of a plurality of places, to a second place so as to obtain a shifted data word, wherein the first place is encrypted using a first encryption parameter and wherein the second place is encrypted using a second encryption parameter, includes a unit for shifting the first place of the data word to the second place of the data word, a unit for re-encrypting the first place from an encryption using the first encryption parameter into an encryption using the second encryption parameter, and a control for controlling the unit for shifting and the unit for re-encryption so that the first place is first shifted to the second place and is then re-encrypted, or that the first place is first re-encrypted and is then shifted to the second place. This ensures that data encrypted either with the first encryption parameter or with the second encryption parameter are always shifted, thus making it harder for attackers to eavesdrop on clear text data.

Abstract: A communication device for transmitting data to a communication partner device includes a transmitter for transmitting transmit data to the communication partner device, a determiner for determining a check value from the transmit data in accordance with a determination specification, a receiver for receiving a verification value from the communication partner device, and a checker configured to compare the check value with the verification value and to provide a fault indication signal as a function of the comparison.

Abstract: In a device for determining a position of a bit error in a bit sequence, a check matrix is used which has a predefined number of rows and a predefined number of columns. The check matrix includes a plurality of square submatrices having a submatrix row number and a submatrix column number corresponding to the predefined number of rows or the predefined number of columns of the check matrix. The device for determining then includes a unit for receiving a bit sequence and a unit for identifying a syndrome using the check matrix and the received bit sequence.

Abstract: A microprocessor configuration includes a data bus for data transfer between functional units. On the bus side, each unit contains an encryption/decryption unit that is controlled synchronously by a random number generator. The configuration permits a relatively high level of security against monitoring of the data transferred via the data bus, with a feasible level of additional circuit complexity.

Abstract: A microprocessor configuration includes a central control and processing unit, a bus having a bus state line and data/address lines, and units connected to the bus. If none of the units is being addressed by the control and processing unit, random data values are transmitted on the data/address lines. Such a process and configuration masks the current profile of the microprocessor configuration with regard to the useful information to be transmitted through the bus.

Abstract: A controller has a receiver for receiving an instruction, the instruction being an executable instruction or a wildcard instruction. A decoder is formed to output a control signal corresponding to the executable instruction responsive to an executable instruction, and to output a switch signal responsive to a received wildcard instruction. Additionally, the controller has a provider for providing a predetermined substitute control signal outputting the predetermined substitute control signal depending on the switch signal.

Abstract: A controller having a receiver for receiving an instruction, a comparator for comparing the received instruction to a predetermined wildcard instruction, the comparator providing a switch signal to a provider for providing a predetermined substitution instruction responsive to the predetermined wildcard instruction. Depending on the switch signal, the provider outputs the received instruction or the other instruction.

Abstract: A shift device for shifting a first place of a data word, which consists of a plurality of places, to a second place so as to obtain a shifted data word, wherein the first place is encrypted using a first encryption parameter and wherein the second place is encrypted using a second encryption parameter, includes a unit for shifting the first place of the data word to the second place of the data word, a unit for re-encrypting the first place from an encryption using the first encryption parameter into an encryption using the second encryption pa- rameter, and a control for controlling the unit for shifting and the unit for re-encryption so that the first place is first shifted to the second place and is then re-encrypted, or that the first place is first re-encrypted and is then shifted to the second place. This ensures that data encrypted either with the first encryption parameter or with the second encryption parameter are always shifted, thus making it harder for attackers to eavesdrop on clear text data.

Abstract: A calculating unit for performing an arithmetic operation with at least two operands, the at least two operands being encrypted, includes an arithmetic-logic unit with a first input for the first encrypted operand, a second input for the second encrypted operand, a third input for an encryption parameter and an output for an encrypted result of the operation, the arithmetic-logic unit being formed so as to operate on the first input, the second input and the third input by means of arithmetic sub-operations, while considering the type of encryption of the operands, such that at the output, an encrypted result is obtained which equals a value that would be obtained if the first operand was subjected to the arithmetic operation in a non-encrypted state and if the second operand would be subjected to the arithmetic operation in a non-encrypted state, and a result obtained was subsequently encrypted, no decryption of the operands being performed in the arithmetic-logic unit.

Abstract: A frequency regulating circuit for the current-consumption-dependent clock supply of a circuit configuration includes a current measuring device for measuring the instantaneous current consumption of the circuit configuration, a controllable clock supply circuit, which can be connected to a clock input of the circuit configuration, and a control device for driving the clock supply circuit based upon the measured current consumption, an increase in the current consumption of the circuit configuration effecting a reduction in the clock frequency at the output of the clock supply circuit. Such a circuit ensures that a maximum permissible current consumption is not exceeded, but, at the same time, makes possible a maximum power of the circuit by a maximum clock frequency.

Abstract: A data bus configuration has a data bus which can be operated in a multiplex mode and to which at least one control station and a reception station are connected. The data bus configuration further has a control bus via which the control station can allocate a logical channel to the reception station.

Abstract: A data processing apparatus comprises a data processing module, which can be operated in a first operating mode with a normal power consumption and a second operating mode, wherein a power consumption of the data processing module in the second operating mode is smaller than the first power consumption or equal to 0. The data processing apparatus further comprises means for signaling a possibility that the data processing module can be placed into the second operating mode. Further, means for providing a time-varying control signal is provided, wherein means feeds means for placing the data processing module from one data operating mode to the other, wherein means for placing is formed to place the data processing module into the other operating mode, when means for signaling signals the possibility and the control signal fulfils a predetermined condition.

Abstract: The built-in self test method enables common and concurrent self testing of the combinatorial logic and the memory of an electronic circuit. The common self test circuit for the logic and the memory performs the self test simultaneously for the logic and for the memory.

Abstract: In a microprocessor configuration, data is temporarily stored in a cache memory or a register bank. A respectively assigned cryptographic unit ensures that the data is encrypted or decrypted when the cache memory or the register bank is accessed. The keyword which is used here is changed if the cache memory or the register no longer contains any valid data to be read out. As a result, an increased protection is obtained against unauthorized monitoring of data and program sequences.