Abstract: A networked computational architecture for provisioning of virtualized computational resources. The architecture is accessible by a client application run on a client device. The architecture includes a hardware layer having a plurality of server devices, each server device having at least one physical processor having a local memory. A resource controller is provided and operable to allocate a plurality of server devices to a client application for data processing and to assign control information to the client application. The control information specifies the required allocation of a data processing workload to each server device allocated to the client application. The architecture is configured such that client applications send the data processing workload directly to each server in accordance with the control information. Thus, a networked architecture is load balanced indirectly without requiring a load balancer to be located in the data path between the client and the server.

Abstract: A system and method of dynamically provisioning virtualised computational resources in a networked computer architecture includes at least one client device operable to run one or more client applications, at least one server device and a resource controller. Each server device comprises one or more physical processors with local memory. Each server device provides a virtual resource layer through which one or more virtual processing resources can be defined and through which the physical processors of the server device can be assigned to the virtual processing resources. In use, one or more virtual processing resources is assigned to a client application for processing of data processing workloads. The resource controller then monitors the utilisation of each virtual processing resource and/or any physical processor assigned to the virtual processing resource. The resource controller can dynamically adjust which, and how many, physical processors are assigned to the virtual processing resource.

Abstract: A finite difference wavefield modeling framework decouples the tasks of physical modeling and hardware-software optimization through the use of a platform-agnostic intermediate representation in the form of a dataflow graph. In at least some embodiments a wavefield simulation method includes specifying a kernel of operations to be applied at each point in a space and representing the kernel as a platform-agnostic dataflow graph. For each of multiple implementation platforms, the method further includes: deriving from the platform-agnostic graph a customized graph for the implementation platform; translating the customized graph into configuration information for the implementation platform; supplying the configuration information to the implementation platform to obtain a wavefield simulator; and employing the wavefield simulator to repeatedly apply said kernel of operations to each point in the space with specified input or output signals.

Abstract: There is provided a method of, and apparatus for, processing a computation on a computing device comprising at least one processor and a memory, the method comprising: storing, in said memory, plural copies of a set of data, each copy of said set of data having a different compression ratio and/or compression scheme; selecting a copy of said set of data; and performing, on a processor, a computation using said selected copy of said set of data. By providing such a method, different compression ratios and/or compression schemes can be selected as appropriate. For example, if high precision is required in a computation, a copy of the set of data can be chosen which has a low compression ratio at the expense of processing time and memory transfer time. In the alternative, if low precision is acceptable, then the speed benefits of a high compression ratio and/or lossy compression scheme may be utilised.

Abstract: Disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph; inserting, on each edge, monitoring hardware to monitor flow of data along the edge. Also disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting the nodes in the graph; inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data for onward transmission to a connected node.

Abstract: A system and method for processing seismic data on one or more co-processor devices that are operatively coupled to a host computing system via a communications channel. The compression of input data transmitted to the co-processor device and/or the size of the storage provided on the co-processor device may enhance the efficiency of the processing of the data on the peripheral device by obviating a bottleneck caused by the relatively slow transfer of data between the host computing system and the co-processor device or by the relatively slow transfer of data within the co-processor device between the co-processor information storage and the co-processor.

Abstract: A method of data compression includes obtaining a data set comprising a sequence of data blocks comprising a predetermined number of data items, partitioning said data set into one or more groups each comprising a predetermined number of data blocks, and performing data compression on one or more groups of data blocks. Data compression is performed by associating a control data item with each of said blocks, generating a control vector comprising the control data items assigned to each of said blocks within a group, removing data blocks comprising entirely data items having said specified value, compressing data blocks comprising at least one data item having a value different from said specified value using a fixed-rate compression scheme, providing a compressed data stream comprising said compressed data blocks, and providing an associated control vector stream to enable control of said compressed data stream.

Abstract: A system and method for processing seismic data on one or more co-processor devices that are operatively coupled to a host computing system via a communications channel. The compression of input data transmitted to the co-processor device and/or the size of the storage provided on the co-processor device may enhance the efficiency of the processing of the data on the peripheral device by obviating a bottleneck caused by the relatively slow transfer of data between the host computing system and the co-processor device or by the relatively slow transfer of data within the co-processor device between the co-processor information storage and the co-processor.

Abstract: There is provided a method of processing an iterative computation on a computing device comprising at least one processor. Embodiments of the method comprises performing, on a processor, an iterative calculation on data in a fixed point numerical format having a scaling factor, wherein the scaling factor is selectively variable for different steps of said calculation in order to prevent overflow and to minimize underflow. By providing such a method, the reliability, precision and flexibility of floating point operations can be achieved whilst using fixed point processing logic. The errors which fixed-point units are usually prone to generate if the range limits are exceeded can be mitigated, whilst still providing the advantage of a significantly reduced logic area to perform the calculations in fixed point.

Abstract: A method and corresponding system is provided for computation utilizing an earth model representation via a computing system having a first processor having access to an earth model dataset. The method includes compressing the earth model dataset at the first processor to generate a look-up table and a set of data indices (i.e., collectively a compressed earth model representation), wherein the look-up table includes quantized data values. By then storing the look-up table in a first level (“fast”) memory, and storing the indices in a second level (“slower,” higher memory capacity) memory, the look-up table and the indices can be accessed to selectively decompress the compressed earth model representation at the first processor such that the computation can be performed efficiently by the first processor.

Abstract: A method is performed at a FPGA coprocessor having memory that stores a plurality of blocks of compressed seismic traces. The method includes: receiving, from a host, a request for processing a predefined set of seismic traces, the request including block location and trace header information; accessing one or more of the blocks of compressed seismic traces from the memory in accordance with the block location information; decompressing each of the one or more accessed blocks into one or more seismic traces thereby forming a plurality of decompressed traces of seismic data; selecting all or a portion of the decompressed traces of seismic data in accordance with the trace header information; processing the selected decompressed traces of seismic data by applying one or more predefined operations to the seismic data; and returning the processed seismic data to the host.

Abstract: A method of data compression includes obtaining a data set comprising a sequence of data blocks comprising a predetermined number of data items, partitioning said data set into one or more groups each comprising a predetermined number of data blocks, and performing data compression on one or more groups of data blocks. Data compression is performed by associating a control data item with each of said blocks, generating a control vector comprising the control data items assigned to each of said blocks within a group, removing data blocks comprising entirely data items having said specified value, compressing data blocks comprising at least one data item having a value different from said specified value using a fixed-rate compression scheme, providing a compressed data stream comprising said compressed data blocks, and providing an associated control vector stream to enable control of said compressed data stream.

Abstract: A system and method for processing seismic data on one or more co-processor devices that are operatively coupled to a host computing system via a communications channel. The compression of input data transmitted to the co-processor device and/or the size of the storage provided on the co-processor device may enhance the efficiency of the processing of the data on the peripheral device by obviating a bottleneck caused by the relatively slow transfer of data between the host computing system and the co-processor device or by the relatively slow transfer of data within the co-processor device between the co-processor information storage and the co-processor.

Abstract: A system and method for processing seismic data on one or more co-processor devices that are operatively coupled to a host computing system via a communications channel. The compression of input data transmitted to the co-processor device and/or the size of the storage provided on the co-processor device may enhance the efficiency of the processing of the data on the peripheral device by obviating a bottleneck caused by the relatively slow transfer of data between the host computing system and the co-processor device or by the relatively slow transfer of data within the co-processor device between the co-processor information storage and the co-processor.

Abstract: A method of generating a hardware design for a pipelined parallel stream processor. The method includes defining a processing operation designating processes to be implemented in hardware as part of said pipelined parallel stream processor and defining a graph representing said processing operation as a parallel structure in the time domain as a function of clock cycles. The method also includes defining the at least one data path and associated latencies of said graph as a set of algebraic linear inequalities, collectively solving the set of linear inequalities for the entire graph, optimizing the at least one data path in the graph using the solved linear inequalities to produce an optimized graph, and utilizing the optimized graph to define an optimized hardware design for implementation in hardware as the pipelined parallel stream processor.

Abstract: There is provided a method for processing data sets in a processor. The processor has a pipelined data path including an input, an output, and at least one discrete stage. The pipeline is configured to enable one or more data sets, each comprising one or more data items, to enter the pipeline from the input, propagate through the pipeline, and exit the pipeline through the output. Each discrete stage represents an operation to be performed on the data item occupying the discrete stage. The method comprises defining one or more non-overlapping sections of the pipeline corresponding to portions of the pipeline occupied by the data items of at least one data set. In addition, the method comprises providing one or more logic units, each dedicated to control the progress of the data items of the at least one data set through the pipeline as the section advances through the pipeline.

Abstract: A method of generating a hardware design for a pipelined parallel stream processor, by defining a hardware processing operation; specifying at least one propagation rule; defining a graph representing the processing operation in the time domain, comprising at least one data path to be implemented as a hardware design and a plurality of parallel branches; each data path having: at least one data path input, output, and discrete object corresponding to a hardware element; each discrete object comprises an input for receiving an input variable, an operator for executing a function on said input variable, and an output variable; optimizing each output from each discrete object in dependence upon the propagation rule to produce an optimised graph; and utilizing the optimised graph to define an optimised hardware design for implementation in said pipelined parallel stream processor.

Abstract: A system and method for compressing and/or decompressing data uses a field programmable gate array (FPGA). In an embodiment, the method includes receiving data at the FPGA device, filtering the received data in a first dimension using a first logic structure of the FPGA device, storing the first filtered data in a memory of the FPGA device, filtering the received data in a second dimension using a second logic structure of the FPGA device, storing the second filtered data in the memory, quantizing the filtered data using a third logic structure of the FPGA device, encoding the quantized data using a fourth logic structure of the FPGA device to compress the data, and storing the encoded compressed data in a memory of the FPGA device.

Abstract: There is provided embodiment of methods of and apparatus for generating a hardware design for a pipelined parallel stream processor.

Abstract: A method of generating a hardware design for a pipelined parallel stream processor, by defining a hardware processing operation; specifying at least one propagation rule; defining a graph representing the processing operation in the time domain, comprising at least one data path to be implemented as a hardware design and a plurality of parallel branches; each data path having: at least one data path input, output, and discrete object corresponding to a hardware element; each discrete object comprises an input for receiving an input variable, an operator for executing a function on said input variable, and an output variable; optimizing each output from each discrete object in dependence upon the propagation rule to produce an optimised graph; and utilizing the optimised graph to define an optimised hardware design for implementation in said pipelined parallel stream processor.