Abstract: Disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph; inserting, on each edge, monitoring hardware to monitor flow of data along the edge. Also disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting the nodes in the graph; inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data for onward transmission to a connected node.

Abstract: A system and method for processing seismic data on one or more co-processor devices that are operatively coupled to a host computing system via a communications channel. The compression of input data transmitted to the co-processor device and/or the size of the storage provided on the co-processor device may enhance the efficiency of the processing of the data on the peripheral device by obviating a bottleneck caused by the relatively slow transfer of data between the host computing system and the co-processor device or by the relatively slow transfer of data within the co-processor device between the co-processor information storage and the co-processor.

Abstract: Embodiments of the invention provide a method and apparatus for generating programmable logic for a hardware accelerator, the method comprising: generating a graph of nodes representing the programmable logic to be implemented in hardware; identifying nodes within the graph that affect external flow control of the programmable logic; retaining the identified nodes and removing or replacing all nodes which do not affect external flow control of the programmable logic in a modified graph; and simulating the modified graph or building a corresponding circuit of the retained nodes.

Abstract: A method and corresponding system is provided for computation utilizing an earth model representation via a computing system having a first processor having access to an earth model dataset. The method includes compressing the earth model dataset at the first processor to generate a look-up table and a set of data indices (i.e., collectively a compressed earth model representation), wherein the look-up table includes quantized data values. By then storing the look-up table in a first level (“fast”) memory, and storing the indices in a second level (“slower,” higher memory capacity) memory, the look-up table and the indices can be accessed to selectively decompress the compressed earth model representation at the first processor such that the computation can be performed efficiently by the first processor.

Abstract: A system and method for processing data on a peripheral device that is operatively coupled to a host computing system via a peripheral bus. The compression of input data transmitted to the peripheral device and/or the size of the storage provided on the peripheral device may enhance the efficiency of the processing of the data on the peripheral device by obviating a bottleneck caused by the relatively slow transfer of data between the host computing system and the peripheral device.

Abstract: There is provided embodiment of methods of generating a hardware design for a pipelined parallel stream processor.

Abstract: A system and method for compressing and/or decompressing data uses a field programmable gate array (FPGA). In an embodiment, the method includes receiving data at the FPGA device, filtering the received data in a first dimension using a first logic structure of the FPGA device, storing the first filtered data in a memory of the FPGA device, filtering the received data in a second dimension using a second logic structure of the FPGA device, storing the second filtered data in the memory, quantizing the filtered data using a third logic structure of the FPGA device, encoding the quantized data using a fourth logic structure of the FPGA device to compress the data, and storing the encoded compressed data in a memory of the FPGA device.

Abstract: There is provided a method of, and apparatus for, processing a computation on a computing device comprising at least one processor and a memory, the method comprising: storing, in said memory, plural copies of a set of data, each copy of said set of data having a different compression ratio and/or compression scheme; selecting a copy of said set of data; and performing, on a processor, a computation using said selected copy of said set of data. By providing such a method, different compression ratios and/or compression schemes can be selected as appropriate. For example, if high precision is required in a computation, a copy of the set of data can be chosen which has a low compression ratio at the expense of processing time and memory transfer time. In the alternative, if low precision is acceptable, then the speed benefits of a high compression ratio and/or lossy compression scheme may be utilised.

Abstract: There is provided a method of processing an iterative computation on a computing device comprising at least one processor. Embodiments of the method comprises performing, on a processor, an iterative calculation on data in a fixed point numerical format having a scaling factor, wherein the scaling factor is selectively variable for different steps of said calculation in order to prevent overflow and to minimise underflow. By providing such a method, the reliability, precision and flexibility of floating point operations can be achieved whilst using fixed point processing logic. The errors which fixed-point units are usually prone to generate if the range limits are exceeded can be mitigated, whilst still providing the advantage of a significantly reduced logic area to perform the calculations in fixed point.

Abstract: A method and system for generating images of a subsurface region of interest. In general, one embodiment of the present invention includes establishing boundary conditions utilizing seismic data and initial conditions which include excitation from source locations in an earth model. Source wavefields are then propagated forward through the earth model to a maximum time, and saved at a plurality of checkpoints sparsely in time and also corresponding boundary values of the source wavefields at each time step are saved. Source wavefields are also propagated backward through the earth model from the maximum time utilizing the plurality of checkpoints when available and the saved boundary values at each time step. Receiver wavefields are propagated backward concurrently through the earth model from the maximum time.

Abstract: A system and method for processing data on a peripheral device that is operatively coupled to a host computing system via a peripheral bus. The compression of input data transmitted to the peripheral device and/or the size of the storage provided on the peripheral device may enhance the efficiency of the processing of the data on the peripheral device by obviating a bottleneck caused by the relatively slow transfer of data between the host computing system and the peripheral device.